DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Derating Timing Tables
Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case
numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be
much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and
voltage multiply the noted numbers with the derating factors provided below.
The junction temperature for the FPGA depends on the power dissipation by the device, the package thermal char-
acteristics (Θ ), and the ambient temperature, as calculated with the following equation:
JA
T
= T
+ (Power * Θ )
JMAX
AMAX JA
The user must determine this temperature and then use it to determine the derating factor based on the following
derating tables: T °C.
J
Table 3-5. Delay Derating Table for Internal Blocks
Power Supply Voltage
T °C
T °C
J
J
Commercial
Industrial
1.14V
0.82
0.82
0.89
0.93
1.00
1.2V
0.77
0.76
0.83
0.87
0.94
1.26V
0.71
0.71
0.78
0.81
0.89
—
—
0
-40
-25
20
25
85
45
105
3-13
LATTICE [ LATTICE SEMICONDUCTOR ]
