DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC External Switching Characteristics (Continued)
Over Recommended Operating Conditions
-5
-4
-3
Parameter
Description
Data Valid Before DQS
Data Valid After DQS
DDR Clock Frequency
Device
All
Min.
0.20
0.20
95
Max.
—
Min.
0.20
0.20
95
Max.
—
Min.
0.20
0.20
95
Max.
—
Units
UI
t
t
f
DQVBS
All
All
—
—
—
UI
DQVAS
200
166
133
MHz
MAX_DDR
Primary and Secondary Clock6
2
f
Frequency for Primary Clock Tree All
—
420
—
—
378
—
—
340
—
MHz
ns
MAX_PRI
Clock Pulse Width for Primary
t
All
1.19
1.19
1.19
W_PRI
Clock
Primary Clock Skew within an I/O
Bank
t
All
—
250
—
300
—
350
ps
SKEW_PRI
1. General timing numbers based on LVCMOS2.5V, 12 mA. Loading of 0 pF.
2. Using LVDS I/O standard.
3. DDR timing numbers based on SSTL I/O.
4. DDR specifications are characterized but not tested.
5. UI is average bit period.
6. Based on a single primary clock.
7. These timing numbers were generated using ispLEVER design tool. Exact performance may vary with design and tool version. The tool
uses internal parameters that have been characterized but are not tested on every device.
Timing v.G 0.30
Figure 3-5. DDR Timings
DQ and DQS Read Timings
DQS
DQ
tDVADQ
tDVEDQ
DQ and DQS Write Timings
DQS
DQ
tDQVBS
tDQVAS
3-15
LATTICE [ LATTICE SEMICONDUCTOR ]
