DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC Internal Switching Characteristics
Over Recommended Operating Conditions
-5
-4
-3
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
PFU/PFF Logic Mode Timing
t
t
t
t
t
t
t
t
t
t
LUT4 Delay (A to D Inputs to F Output)
LUT6 Delay (A to D Inputs to OFX Output)
Set/Reset to Output of PFU
—
—
0.25
0.40
0.81
—
—
—
0.31
0.48
0.98
—
—
—
0.36
0.56
1.14
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LUT4_PFU
LUT6_PFU
LSR_PFU
SUM_PFU
HM_PFU
—
—
—
Clock to Mux (M0,M1) Input Setup Time
Clock to Mux (M0,M1) Input Hold Time
Clock to D Input Setup Time
0.12
-0.05
0.12
-0.03
—
0.14
-0.06
0.14
-0.03
—
0.16
-0.06
0.16
-0.04
—
—
—
—
—
—
—
SUD_PFU
HD_PFU
Clock to D Input Hold time
—
—
—
Clock to Q Delay, D-type Register Configuration
Clock to Q Delay Latch Configuration
D to Q Throughput Delay when Latch is Enabled
0.36
0.48
0.50
0.44
0.58
0.60
0.51
0.68
0.69
CK2Q_PFU
LE2Q_PFU
LD2Q_PFU
—
—
—
—
—
—
PFU Dual Port Memory Mode Timing
t
t
t
t
t
t
t
Clock to Output
—
0.36
—
—
0.44
—
—
0.51
—
ns
ns
ns
ns
ns
ns
ns
CORAM_PFU
SUDATA_PFU
HDATA_PFU
Data Setup Time
-0.20
0.26
-0.51
0.64
-0.24
0.30
-0.24
0.31
-0.62
0.77
-0.29
0.36
-0.28
0.36
-0.72
0.90
-0.34
0.42
Data Hold Time
—
—
—
Address Setup Time
Address Hold Time
—
—
—
SUADDR_PFU
HADDR_PFU
SUWREN_PFU
HWREN_PFU
—
—
—
Write/Read Enable Setup Time
Write/Read Enable Hold Time
—
—
—
—
—
—
PIC Timing
PIO Input/Output Buffer Timing
t
t
Input Buffer Delay
Output Buffer Delay
—
—
0.56
1.92
—
—
0.67
2.31
—
—
0.78
2.69
ns
ns
IN_PIO
OUT_PIO
IOLOGIC Input/Output Timing
t
t
t
t
t
t
t
Input Register Setup Time (Data Before Clock)
Input Register Hold Time (Data after Clock)
Output Register Clock to Output Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
Set/Reset Setup Time
0.90
0.62
—
—
—
1.08
0.74
—
—
—
1.26
0.87
—
—
—
ns
ns
ns
ns
ns
ns
ns
SUI_PIO
HI_PIO
0.33
—
0.40
—
0.46
—
COO_PIO
SUCE_PIO
HCE_PIO
SULSR_PIO
HLSR_PIO
-0.10
0.12
0.18
-0.15
-0.12
0.14
0.21
-0.18
-0.14
0.17
0.25
-0.21
—
—
—
—
—
—
Set/Reset Hold Time
—
—
—
EBR Timing
t
t
t
t
t
t
t
t
Clock to Output from Address or Data
Clock to Output from EBR output Register
Setup Data to EBR Memory
—
3.64
0.74
—
—
4.37
0.88
—
—
5.10
1.03
—
ns
ns
ns
ns
ns
ns
ns
ns
CO_EBR
—
—
—
COO_EBR
-0.29
0.37
-0.29
0.37
-0.18
0.23
-0.35
0.44
-0.35
0.45
-0.22
0.28
-0.41
0.52
-0.41
0.52
-0.26
0.33
SUDATA_EBR
HDATA_EBR
SUADDR_EBR
HADDR_EBR
SUWREN_EBR
HWREN_EBR
Hold Data to EBR Memory
—
—
—
Setup Address to EBR Memory
—
—
—
Hold Address to EBR Memory
—
—
—
Setup Write/Read Enable to EBR Memory
Hold Write/Read Enable to EBR Memory
—
—
—
—
—
—
3-16
LATTICE [ LATTICE SEMICONDUCTOR ]
