DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
LatticeECP/EC External Switching Characteristics
Over Recommended Operating Conditions
-5
-4
-3
Parameter
Description
Device
Min.
Max.
Min.
Max.
Min.
Max.
Units
General I/O Pin Parameters (Using Primary Clock without PLL)1
LFEC1
—
5.09
5.71
5.60
5.47
5.67
5.89
6.19
—
—
6.11
6.85
6.72
6.57
6.81
7.07
7.42
—
—
7.13
7.99
7.84
7.66
7.94
8.25
8.66
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LFEC3
—
—
—
LFEC6
—
—
—
Clock to Output - PIO Output
Register
7
t
t
t
t
LFEC10
LFEC15
LFEC20
LFEC33
LFEC1
—
—
—
CO
—
—
—
—
—
—
—
—
—
-0.08
-0.70
-0.63
-0.43
-0.70
-0.88
-1.12
2.19
2.80
2.69
2.56
2.76
2.99
3.28
3.36
2.74
2.81
3.01
2.74
2.56
2.32
-1.31
-0.70
-0.80
-0.93
-0.73
-0.51
-0.22
-0.10
-0.84
-0.76
-0.52
-0.84
-1.06
-1.34
2.62
3.36
3.23
3.08
3.32
3.58
3.93
4.03
3.29
3.37
3.61
3.29
3.07
2.79
-1.57
-0.83
-0.96
-1.12
-0.88
-0.61
-0.26
-0.12
-0.98
-0.89
-0.61
-0.98
-1.24
-1.56
3.06
3.92
3.77
3.59
3.87
4.18
4.59
4.70
3.84
3.93
4.21
3.83
3.58
3.25
-1.83
-0.97
-1.12
-1.30
-1.02
-0.71
-0.30
LFEC3
—
—
—
LFEC6
—
—
—
Clock to Data Setup - PIO Input
Register
7
LFEC10
LFEC15
LFEC20
LFEC33
LFEC1
—
—
—
SU
—
—
—
—
—
—
—
—
—
—
—
—
LFEC3
—
—
—
LFEC6
—
—
—
Clock to Data Hold - PIO Input
Register
7
LFEC10
LFEC15
LFEC20
LFEC33
LFEC1
—
—
—
H
—
—
—
—
—
—
—
—
—
—
—
—
LFEC3
—
—
—
LFEC6
—
—
—
Clock to Data Setup - PIO Input
Register with Data Input Delay
7
LFEC10
LFEC15
LFEC20
LFEC33
LFEC1
—
—
—
SU_DEL
—
—
—
—
—
—
—
—
—
—
—
—
LFEC3
—
—
—
LFEC6
—
—
—
Clock to Data Hold - PIO Input
Register with Input Data Delay
tH_DEL7
LFEC10
LFEC15
LFEC20
LFEC33
—
—
—
—
—
—
—
—
—
—
—
—
Clock Frequency of I/O and PFU
Register
2
f
All
—
420
—
378
—
340
Mhz
MAX_IO
DDR I/O Pin Parameters3, 4, 5
t
t
Data Valid After DQS (DDR Read) All
Data Hold After DQS (DDR Read) All
—
0.19
—
—
0.19
—
—
0.19
—
UI
UI
DVADQ
DVEDQ
0.67
0.67
0.67
3-14
LATTICE [ LATTICE SEMICONDUCTOR ]
