Architecture
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
IPexpress™
The user can access the sysDSP block via the IPexpress configuration tool, included with the ispLEVER design
tool suite. IPexpress has options to configure each DSP module (or group of modules) or through direct HDL
instantiation. Additionally Lattice has partnered Mathworks to support instantiation in the Simulink tool, which is a
Graphical Simulation Environment. Simulink works with ispLEVER and dramatically shortens the DSP design cycle
in Lattice FPGAs.
Optimized DSP Functions
Lattice provides a library of optimized DSP IP functions. Some of the IPs planned for LatticeECP DSP are: Bit Cor-
relators, Fast Fourier Transform, Finite Impulse Response (FIR) Filter, Reed-Solomon Encoder/ Decoder, Turbo
Encoder/Decoders and Convolutional Encoder/Decoder. Please contact Lattice to obtain the latest list of available
DSP IPs.
Resources Available in the LatticeECP Family
Table 2-9 shows the maximum number of multipliers for each member of the LatticeECP family. Table 2-10 shows
the maximum available EBR RAM Blocks in each of the LatticeECP family. EBR blocks, together with Distributed
RAM can be used to store variables locally for the fast DSP operations.
Table 2-9. Number of DSP Blocks in LatticeECP Family
Device
LFECP6
LFECP10
LFECP15
LFECP20
LFECP33
DSP Block
9x9 Multiplier
18x18 Multiplier
36x36 Multiplier
4
5
6
7
8
32
40
48
56
64
16
20
24
28
32
4
5
6
7
8
Table 2-10. Embedded SRAM in LatticeECP Family
Total EBR SRAM
(Kbits)
Device
LFECP6
LFECP10
LFECP15
LFECP20
LFECP33
EBR SRAM Block
10
30
38
46
54
92
276
350
424
498
DSP Performance of the LatticeECP Family
Table 2-11 lists the maximum performance in millions of MAC operations per second (MMAC) for each member of
the LatticeECP family.
Table 2-11. DSP Block Performance of LatticeECP Family
DSP Performance
Device
LFECP6
LFECP10
LFECP15
LFECP20
LFECP33
DSP Block
MMAC
3680
4600
5520
6440
7360
4
5
6
7
8
2-20
LATTICE [ LATTICE SEMICONDUCTOR ]
