Architecture
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Table 2-12. PIO Signal List
Name
Type
Description
CE0, CE1
CLK0, CLK1
LSR
Control from the core
Control from the core
Control from the core
Control from routing
Input to the core
Clock enables for input and output block FFs.
System clocks for input and output blocks.
Local Set/Reset.
GSRN
Global Set/Reset (active low).
INCK
Input to Primary Clock Network or PLL reference inputs.
DQS signal from logic (routing) to PIO.
DQS
Input to PIO
INDD
Input to the core
Unregistered data input to core.
INFF
Input to the core
Registered input on positive edge of the clock (CLK0).
DDRX registered inputs to the core.
IPOS0, IPOS1
ONEG0
OPOS0,
OPOS1 ONEG1
TD
Input to the core
Control from the core
Control from the core
Tristate control from the core
Tristate control from the core
Output signals from the core for SDR and DDR operation.
Output signals from the core for DDR operation
Signals to Tristate Register block for DDR operation.
Tristate signal from the core used in SDR operation.
DDRCLKPOL
Control from clock polarity bus Controls the polarity of the clock (CLK0) that feed the DDR input block.
Figure 2-25. DQS Routing
PADA "T"
LVDS Pair
PIO A
PIO B
PIO A
PADB "C"
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
Assigned
DQS Pin
PADA "T"
sysIO
Buffer
PIO A
DQS
Delay
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PIO A
PADA "T"
LVDS Pair
PADB "C"
PIO B
PADA "T"
LVDS Pair
PADB "C"
PIO A
PIO B
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
2-22
LATTICE [ LATTICE SEMICONDUCTOR ]
