Architecture
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Input Register Block
The input register block contains delay elements and registers that can be used to condition signals before they are
passed to the device core. Figure 2-26 shows the diagram of the input register block.
Input signals are fed from the sysI/O buffer to the input register block (as signal DI). If desired the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), a clock (INCK) and
in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first
passes through an optional delay block. This delay, if selected, reduces input-register hold-time requirement when
using a global clock.
The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the
registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used
to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.
These two data streams are synchronized with the system clock before entering the core. Further discussion on
this topic is in the DDR Memory section of this data sheet.
Figure 2-27 shows the input register waveforms for DDR operation and Figure 2-28 shows the design tool primi-
tives. The SDR/SYNC registers have reset and clock enable available.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to system clock domain. For further discussion on this topic,
see the DDR Memory section of this data sheet.
Figure 2-26. Input Register Diagram
DI
(From sysIO
Buffer)
INCK
INDD
Delay Block
Fixed Delay
SDR & Sync
Registers
DDR Registers
D0
D2
To Routing
Q
D
Q
D
D
IPOS0
IPOS1
D-Type
/LATCH
D-Type
D1
Q
D
Q
Q
D
D-Type
/LATCH
D-Type
D-Type
DQS Delayed
(From DQS
Bus)
CLK0
(From Routing)
DDRCLKPOL
(From DDR
Polarity Control Bus)
2-23
LATTICE [ LATTICE SEMICONDUCTOR ]
