Architecture
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
Figure 2-20. MAC sysDSP Element
Shift Register B In
Shift Register A In
m
Multiplicand
Multiplier
m
Accumulator
m
n
m+n+16 bits
(default)
n
Multiplier
m
n
Input Data
Register A
n
Output
m+n+16 bits
(default)
x
m+n
(default)
Input Data
Register B
Pipeline
Register
n
n
SignedAB
Addn
Input
Register
Pipeline
Register
Overflow
signal
To
Accumulator
Input
Register
Pipeline
Register
To
Accumulator
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
Accumsload
Input
Register
Pipeline
Register
To
Accumulator
RST(RST0,RST1,RST2,RST3)
Shift Register B Out
Shift Register A Out
MULTADD sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-21
shows the MULTADD sysDSP element.
Figure 2-21. MULTADD
Shift Register B In
Shift Register A In
m
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
Multiplicand A0
m
RST(RST0,RST1,RST2,RST3)
m
n
Multiplier B0
n
Multiplier
Input Data
Register A
m
n
n
x
m+n
Input Data
Register B
(default)
Pipeline
Register
m
Add/Sub
n
Multiplicand A1
Multiplier B1
m
Output
m+n+1
(default)
m+n+1
(default)
m
n
Multiplier
m+n
(default)
Input Data
Register A
m
n
n
x
Input Data
Register B
Pipeline
Register
m
n
Signed
Addn
Input
Register
Pipeline
Register
Reg
Pipe
To Add/Sub
To Add/Sub
Input
Pipeline
Pipe
Register
Register
Reg
Shift Register B Out
Shift Register A Out
2-17
LATTICE [ LATTICE SEMICONDUCTOR ]
