Architecture
LatticeECP/EC Family Data Sheet
Lattice Semiconductor
MULTADDSUM sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/
subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction
are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-22 shows
the MULTADDSUM sysDSP element.
Figure 2-22. MULTADDSUM
Shift Register B In
Shift Register A In
m
Multiplicand A0
m
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
m
n
Multiplier B0
n
Multiplier
Input Data
Register A
m
n
RST(RST0,RST1,RST2,RST3)
m+n
(default)
n
x
Input Data
Register B
Pipeline
Register
m
Add/Sub0
n
Multiplicand A1
Multiplier B1
m
m+n
(default)
m
n
Multiplier
Input Data
Register A
n
n
m+n+1
n
x
Input Data
Register B
SUM
Pipeline
Register
Output
Multiplicand A2
Multiplier B2
m
m
m
m+n+2
m+n+2
n
n
Multiplier
m
n
Input Data
Register A
m+n
(default)
n
x
m+n+1
Input Data
Register B
Pipeline
Register
m
Add/Sub1
n
Multiplicand A3
Multiplier B3
m
m+n
(default)
m
n
Multiplier
Input Data
Register A
m
n
n
x
Input Data
Register B
Pipeline
Register
m
n
Signed
Addn0
Addn1
Input
Register
Pipeline
Register
To Add/Sub0, Add/Sub1
To Add/Sub0
Input
Register
Pipeline
Register
Input
Register
Pipeline
Register
To Add/Sub1
Shift Register B Out
Shift Register A Out
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset
and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)
one clock is selected for each input register, pipeline register and output register. Similarly Clock enable (CE) and
Reset (RST) are selected from their four respective sources (CE0, CE1, CE2, CE3 and RST0, RST1, RST2, RST3)
at each input register, pipeline register and output register.
2-18
LATTICE [ LATTICE SEMICONDUCTOR ]
