Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000Z Internal Timing Parameters
Over Recommended Operating Conditions
-35
-37
-42
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
In/Out Delays
t
t
t
t
t
t
Input Buffer Delay
—
—
—
—
—
—
0.75
2.25
1.60
0.75
2.25
1.35
—
—
—
—
—
—
0.80
2.25
1.60
0.90
2.25
1.35
—
—
—
—
—
—
0.75
2.30
1.95
0.90
2.50
2.50
ns
ns
ns
ns
ns
ns
IN
Global OE Pin Delay
GOE
GCLK_IN
BUF
EN
Global Clock Input Buffer Delay
Delay through Output Buffer
Output Enable Time
Output Disable Time
DIS
Routing/GLB Delays
t
t
t
t
t
t
Delay through GRP
—
—
—
—
—
—
1.60
0.65
0.91
0.05
0.40
0.25
—
—
—
—
—
—
1.60
0.75
1.00
0.00
0.40
0.25
—
—
—
—
—
—
2.15
0.85
1.00
0.00
0.40
0.65
ns
ns
ns
ns
ns
ns
ROUTE
MCELL
INREG
FBK
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
5-PT Bypass Propagation Delay
Macrocell Propagation Delay
PDb
PDi
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
D-Register Setup Time (Global Clock)
D-Register Setup Time (Product Term Clock)
T-Register Setup Time (Global Clock)
T-register Setup Time (Product Term Clock)
D-Register Hold Time
0.80
1.35
1.00
1.55
1.40
1.40
0.94
1.45
1.06
0.88
—
—
—
0.95
1.95
1.15
1.75
1.55
1.55
0.90
1.45
1.20
1.00
—
—
—
0.90
1.90
1.10
2.10
1.80
1.80
1.50
1.45
1.10
1.00
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S
S_PT
ST
—
—
—
—
—
—
ST_PT
H
—
—
—
T-Resister Hold Time
—
—
—
HT
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
—
—
—
SIR
—
—
—
SIR_PT
HIR
—
—
—
—
—
—
HIR_PT
COi
0.65
—
0.70
—
0.65
—
1.00
0.00
0.80
1.55
1.40
—
2.00
0.00
0.95
1.95
1.80
—
2.00
0.00
0.90
1.90
1.80
—
CES
CEH
SL
Clock Enable Hold Time
—
—
—
Latch Setup Time (Global Clock)
—
—
—
Latch Setup Time (Product Term Clock)
Latch Hold Time
—
—
—
SL_PT
HL
—
—
—
Latch Gate to Output/Feedback MUX Time
0.40
0.33
0.33
GOi
Propagation Delay through Transparent Latch to Output/
Feedback MUX
t
—
0.30
—
0.25
—
0.25
ns
PDLi
t
t
Asynchronous Reset or Set to Output/Feedback MUX Delay
Asynchronous Reset or Set Recovery Delay
—
—
0.28
2.00
—
—
0.28
1.67
—
—
1.27
1.80
ns
ns
SRi
SRR
Control Delays
t
t
t
t
GLB PT Clock Delay
—
—
—
—
1.30
1.50
1.10
1.22
—
—
—
—
1.50
1.70
1.83
2.02
—
—
—
—
1.55
1.55
1.83
1.83
ns
ns
ns
ns
BCLK
PTCLK
BSR
Macrocell PT Clock Delay
GLB PT Set/Reset Delay
Macrocell PT Set/Reset Delay
PTSR
31
LATTICE [ LATTICE SEMICONDUCTOR ]
