Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4000Z Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
-45
-5
-75
Parameter
Description
Min. Max. Min. Max. Min. Max. Units
In/Out Delays
t
t
t
t
t
t
Input Buffer Delay
—
—
—
—
—
—
0.95
3.00
1.95
1.10
2.50
2.50
—
—
—
—
—
—
1.25
3.50
2.05
1.00
2.50
2.50
—
—
—
—
—
—
1.80
4.30
2.15
1.30
2.70
2.70
ns
ns
ns
ns
ns
ns
IN
Global OE Pin Delay
GOE
GCLK_IN
BUF
EN
Global Clock Input Buffer Delay
Delay through Output Buffer
Output Enable Time
Output Disable Time
DIS
Routing/GLB Delays
t
t
t
t
t
t
Delay through GRP
—
—
—
—
—
—
2.25
0.65
1.00
0.35
0.20
0.45
—
—
—
—
—
—
2.05
0.65
1.00
0.05
0.70
0.65
—
—
—
—
—
—
2.50
1.00
1.00
0.05
1.90
1.00
ns
ns
ns
ns
ns
ns
ROUTE
MCELL
INREG
FBK
Macrocell Delay
Input Buffer to Macrocell Register Delay
Internal Feedback Delay
5-PT Bypass Propagation Delay
Macrocell Propagation Delay
PDb
PDi
Register/Latch Delays
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
D-Register Setup Time (Global Clock)
D-Register Setup Time (Product Term Clock)
T-Register Setup Time (Global Clock)
T-register Setup Time (Product Term Clock)
D-Register Hold Time
1.00
2.10
1.20
2.30
1.90
1.90
1.30
1.45
1.30
1.00
—
—
—
1.10
1.90
1.30
2.10
1.90
1.90
1.10
1.45
1.50
1.00
—
—
—
1.35
2.45
1.55
2.75
3.15
3.15
0.75
1.45
1.95
1.18
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
S
S_PT
ST
—
—
—
—
—
—
ST_PT
H
—
—
—
T-Resister Hold Time
—
—
—
HT
D-Input Register Setup Time (Global Clock)
D-Input Register Setup Time (Product Term Clock)
D-Input Register Hold Time (Global Clock)
D-Input Register Hold Time (Product Term Clock)
Register Clock to Output/Feedback MUX Time
Clock Enable Setup Time
—
—
—
SIR
—
—
—
SIR_PT
HIR
—
—
—
—
—
—
HIR_PT
COi
0.75
—
1.15
—
1.05
—
2.00
0.00
1.00
2.10
2.00
—
2.00
0.00
1.00
1.90
2.00
—
2.00
0.00
1.65
2.15
1.17
—
CES
CEH
SL
Clock Enable Hold Time
—
—
—
Latch Setup Time (Global Clock)
—
—
—
Latch Setup Time (Product Term Clock)
Latch Hold Time
—
—
—
SL_PT
HL
—
—
—
Latch Gate to Output/Feedback MUX Time
0.33
0.33
0.33
GOi
Propagation Delay through Transparent Latch to Output/
Feedback MUX
t
—
0.25
—
0.25
—
0.25
ns
PDLi
t
t
Asynchronous Reset or Set to Output/Feedback MUX Delay
Asynchronous Reset or Set Recovery Delay
—
—
0.97
1.80
—
—
0.97
1.80
—
—
0.28
1.67
ns
ns
SRi
SRR
Control Delays
t
t
t
t
t
GLB PT Clock Delay
—
—
—
—
—
1.55
1.55
1.83
1.83
4.30
—
—
—
—
—
1.55
1.55
1.83
1.83
4.20
—
—
—
—
—
1.25
1.25
1.83
2.72
3.50
ns
ns
ns
ns
ns
BCLK
PTCLK
BSR
Macrocell PT Clock Delay
GLB PT Set/Reset Delay
Macrocell PT Set/Reset Delay
Global PT OE Delay
PTSR
GPTOE
33