Specifications ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
TEST4
COND.
-180
-150
-135
DESCRIPTION1
UNITS
2
PARAMETER
#
MIN. MAX. MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Prop. Delay, 4PT Bypass, ORP Bypass
Data Prop. Delay
Clk Frequency with Internal Feedback 3
–
5.0
7.5
–
–
–
5.5
8.0
–
–
–
7.5
10.0
–
ns
ns
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
2
3
4
5
6
7
8
9
–
180
125
200
154
111
167
3.0
–
137
100
167
4.0
–
MHz
MHz
MHz
ns
1
Clk Frequency with Ext. Feedback (tsu2 + tco1
)
–
–
–
–
Clk Frequency, Max. Toggle
–
–
–
–
GLB Reg Setup Time before Clk, 4 PT Bypass 3.0
–
–
–
A
–
GLB Reg. Clk to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clk, 4 PT Bypass
GLB Reg. Setup Time before Clk
–
0.0
4.0
–
4.0
–
4.5
–
4.5
–
ns
0.0
4.5
–
0.0
5.5
–
ns
–
–
–
–
ns
–
10 GLB Reg. Clk to Output Delay
11 GLB Reg. Hold Time after Clk
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
4.5
–
5.0
–
5.5
–
ns
–
0.0
–
0.0
–
0.0
–
ns
A
–
7.0
–
8.0
–
10.0
–
ns
4.0
–
4.5
–
5.0
–
ns
B
C
B
C
–
14 Input to Output Enable
10.0
10.0
5.0
5.0
–
11.0
11.0
5.0
5.0
–
12.0
12.0
6.0
6.0
–
ns
15 Input to Output Disable
–
–
–
ns
16 Global OE Output Enable
–
–
–
ns
17 Global OE Output Disable
–
–
–
ns
18 Ext. Synchronous Clk Pulse Duration, High
19 Ext. Synchronous Clk Pulse Duration, Low
2.5
2.5
3.0
3.0
3.0
3.0
ns
–
–
–
–
ns
twl
Table 2-0030B-180/2032
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
5
LATTICE [ LATTICE SEMICONDUCTOR ]
