Specifications ispLSI 2032/A
External Timing Parameters
Over Recommended Operating Conditions
TEST4
COND.
-110
-80
DESCRIPTION1
UNITS
2
PARAMETER
#
MIN. MAX. MIN. MAX.
A
A
A
–
1
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback3
–
–
10.0
13.0
–
–
–
15.0
18.5
–
ns
ns
tpd1
tpd2
fmax
fmax (Ext.)
fmax (Tog.)
tsu1
tco1
th1
tsu2
tco2
th2
tr1
trw1
tptoeen
tptoedis
tgoeen
tgoedis
twh
2
3
4
5
6
7
8
9
111
77.0
125
5.5
–
84.0
57.0
83.0
7.5
–
MHz
MHz
MHz
ns
1
Clock Frequency with External Feedback(tsu2 + tco1
)
–
–
–
Clock Frequency, Max. Toggle
–
–
–
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
GLB Reg. Setup Time before Clock
–
–
A
–
5.5
–
8.0
–
ns
0.0
7.5
–
0.0
9.5
–
ns
–
–
–
ns
–
10 GLB Reg. Clock to Output Delay
11 GLB Reg. Hold Time after Clock
12 Ext. Reset Pin to Output Delay
13 Ext. Reset Pulse Duration
6.5
–
9.5
–
ns
–
0.0
–
0.0
–
ns
A
–
13.5
–
19.5
–
ns
6.5
–
10.0
–
ns
B
C
B
C
–
14 Input to Output Enable
14.5
14.5
7.0
7.0
–
24.0
24.0
12.0
12.0
–
ns
15 Input to Output Disable
–
–
ns
16 Global OE Output Enable
–
–
ns
17 Global OE Output Disable
–
–
ns
18 External Synchronous Clock Pulse Duration, High
19 External Synchronous Clock Pulse Duration, Low
4.0
4.0
6.0
6.0
ns
–
–
–
ns
twl
Table 2-0030B-110/2032
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
6