Specifications ispLSI 2032/A
Functional Block Diagram
Figure 1. ispLSI 2032/A Functional Block Diagram
GOE 0
I/O 31
I/O 0
I/O 1
I/O 30
A0
A7
I/O 29
I/O 28
I/O 2
I/O 3
I/O 27
I/O 26
I/O 4
I/O 5
Global Routing Pool
(GRP)
A1
A6
A5
A4
I/O 6
I/O 25
I/O 24
I/O 7
I/O 23
I/O 22
I/O 21
I/O 20
I/O 8
I/O 9
I/O 10
A2
I/O 11
I/O 12
I/O 13
I/O 19
I/O 18
I/O 17
I/O 16
I/O 14
A3
I/O 15
SDI/IN 0
SDO/IN 1
MODE
ispEN
Y0
*Y1/RESET
SCLK/Y2
Notes:
*Y1 and RESET are multiplexed on the same pin
0139B(1)isp/2000
The devices also have 32 I/O cells, each of which is GLBs. Delays through the GRP have been equalized to
directly connected to an I/O pin. Each I/O cell can be minimize timing skew.
individually programmed to be a combinatorial input,
Clocks in the ispLSI 2032 and 2032A devices are se-
output or bi-directional I/O pin with 3-state control. The
lected using the dedicated clock pins. Three dedicated
signal levels are TTL compatible voltages and the output
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
drivers can source 4 mA or sink 8 mA. Each output can
selected on a GLB basis. The asynchronous or Product
be programmed independently for fast or slow output
TermclockcanbegeneratedinanyGLBforitsownclock.
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
toasetof32universal I/Ocellsby theORP. EachispLSI
2032 and 2032A device contains one Megablock.
The GRP has as its inputs, the outputs from all of the
GLBs andallof theinputs from thebi-directionalI/O cells.
All of these signals are made available to the inputs of the
2
LATTICE [ LATTICE SEMICONDUCTOR ]
