Specifications ispLSI 2032/A
Internal Timing Parameters1
Over Recommended Operating Conditions
-110
-80
2
PARAMETER
Inputs
#
DESCRIPTION
UNITS
MIN. MAX. MIN. MAX.
20 Input Buffer Delay
–
–
1.7
3.4
–
–
2.2
4.8
ns
ns
t
t
io
21 Dedicated Input Delay
din
GRP
grp
GLB
22 GRP Delay
–
1.7
–
2.6
ns
t
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
25 1 Product Term/XOR Path Delay
–
–
4.9
4.8
6.2
6.8
7.5
0.1
–
–
–
7.2
7.2
8.8
9.2
10.2
0.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
4ptbpc
4ptbpr
1ptxor
20ptxor
xoradj
gbp
–
–
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay3
–
–
–
–
28 GLB Register Bypass Delay
–
–
29 GLB Register Setup Time befor Clock
30 GLB Register Hold Time after Clock
31 GLB Register Clock to Output Delay
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
0.5
4.0
–
0.1
6.0
–
gsu
–
–
gh
0.6
1.8
5.9
7.1
0.4
2.2
8.8
12.8
gco
–
–
gro
–
–
ptre
–
–
ptoe
ptck
4.0 7.0 5.5 9.5
ORP
36 ORP Delay
–
–
1.5
0.5
–
–
2.1
0.6
ns
ns
t
t
orp
37 ORP Bypass Delay
orpbp
Outputs
38 Output Buffer Delay
–
–
–
–
–
–
–
–
–
–
2.4
10.0
6.4
ns
ns
ns
ns
ns
t
t
t
t
t
ob
1.2
10.0
4.0
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
sl
oen
odis
goe
6.4
4.0
5.6
3.0
Clocks
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
3.2
3.2
4.6 4.6
4.6 4.6
ns
ns
t
t
gy0
3.2
3.2
gy1/2
Global Reset
45 Global Reset to GLB
–
–
12.8
Table 2-0036C-110/2032
ns
t
gr
9.0
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
8
LATTICE [ LATTICE SEMICONDUCTOR ]
