Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
IEEE 1149.1-Compliant Boundary Scan Testability
All LatticeECP2/M devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant Test
Access Port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a
serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to
be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for verification.The test
access port consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage
V
and can operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards.
CCJ
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
Device Configuration
All LatticeECP2/M devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration, and the sysCONFIG port, support both byte-wide and serial configuration,
including the standard SPI Flash interface. The TAP supports both the IEEE Standard 1149.1 Boundary Scan
specification and the IEEE Standard 1532 In- System Configuration specification. The sysCONFIG port is a 20-pin
interface with six I/Os used as dedicated pins with the remainder used as dual-use pins. See Lattice technical note
number TN1108, LatticeECP2 sysCONFIG Usage Guide for more information about using the dual-use pins as
general purpose I/Os.
On power-up, the FPGA SRAM is ready to be configured using the selected sysCONFIG port. Once a configuration
port is selected, it will remain active throughout that configuration cycle.The IEEE 1149.1 port can be activated any
time after power-up by sending the appropriate command through the TAP port.
Enhanced Configuration Option
LatticeECP2/M devices have enhanced configuration features such as: decryption support, TransFR™ I/O and
dual boot image support.
1. Decryption Support
LatticeECP2/M devices provide on-chip, One Time Programmable (OTP) non-volatile key storage to support
decryption of a 128-bit AES encrypted bitstream, securing designs and deterring design piracy.
2. TransFR (Transparent Field Reconfiguration)
TransFR I/O (TFR) is a unique Lattice technology that allows users to update their logic in the field without
interrupting system operation using a single ispVM® command. TransFR I/O allows I/O states to be frozen dur-
ing device configuration. This allows the device to be field updated with a minimum of system disruption and
downtime. See Lattice technical note number TN1087, Minimizing System Interruption During Configuration
Using TransFR Technology, for details.
3. Dual Boot Image Support
Dual boot images are supported for applications requiring reliable remote updates of configuration data for the
system FPGA. After the system is running with a basic configuration, a new boot image can be downloaded
remotely and stored in a separate location in the configuration storage device. Any time after the update the
LatticeECP2/M can be re-booted from this new configuration file. If there is a problem, such as corrupt data
during download or incorrect version number with this new boot image, the LatticeECP2/M device can revert
back to the original backup configuration and try again. This all can be done without power cycling the system.
For more information about device configuration, please see the list of additional technical documentation at the
end of this data sheet.
Software Error Detect (SED) Support
LatticeECP2/M devices have dedicated logic to perform CRC checks. During configuration, the configuration data
bitstream can be checked with the CRC logic block. In addition, the LatticeECP2 device can also be programmed
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LATTICE [ LATTICE SEMICONDUCTOR ]
