Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Table 2-14. Supported Output Standards
Output Standard
Single-ended Interfaces
LVTTL
Drive
V
(Nom.)
CCIO
4mA, 8mA, 12mA, 16mA, 20mA
3.3
LVCMOS33
4mA, 8mA, 12mA 16mA, 20mA
3.3
2.5
1.8
1.5
1.2
—
LVCMOS25
4mA, 8mA, 12mA, 16mA, 20mA
LVCMOS18
4mA, 8mA, 12mA, 16mA
LVCMOS15
4mA, 8mA
LVCMOS12
2mA, 6mA
LVCMOS33, Open Drain
LVCMOS25, Open Drain
LVCMOS18, Open Drain
LVCMOS15, Open Drain
LVCMOS12, Open Drain
PCI33
4mA, 8mA, 12mA 16mA, 20mA
4mA, 8mA, 12mA 16mA, 20mA
—
4mA, 8mA, 12mA 16mA
—
4mA, 8mA
2mA, 6mA
N/A
—
—
3.3
1.8
1.5
3.3
2.5
1.8
HSTL18 Class I, II
HSTL15 Class I
N/A
N/A
SSTL3 Class I, II
SSTL2 Class I, II
SSTL18 Class I, II
Differential Interfaces
Differential SSTL3, Class I, II
Differential SSTL2, Class I, II
Differential SSTL18, Class I, II
Differential HSTL18, Class I, II
Differential HSTL15, Class I
LVDS
MLVDS1
BLVDS1
LVPECL1
RSDS1
N/A
N/A
N/A
N/A
3.3
2.5
1.8
1.8
1.5
2.5
2.5
2.5
3.3
2.5
3.3
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LVCMOS33D1
4mA, 8mA, 12mA, 16mA, 20mA
1. Emulated with external resistors. For more detail, please see information regarding additional technical documentation at
the end of this data sheet.
Hot Socketing
LatticeECP2/M devices have been carefully designed to ensure predictable behavior during power-up and power-
down. During power-up and power-down sequences, the I/Os remain in tri-state until the power supply voltage is
high enough to ensure reliable operation. In addition, leakage into I/O pins is controlled within specified limits. This
allows for easy integration with the rest of the system. These capabilities make the LatticeECP2/M ideal for many
multiple power supply and hot-swap applications.
2-45
LATTICE [ LATTICE SEMICONDUCTOR ]
