LatticeECP2/M Family Data Sheet
DC and Switching Characteristics
February 2008
Data Sheet DS1006
Absolute Maximum Ratings1, 2, 3
Supply Voltage V . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V
CC
Supply Voltage V
. . . . . . . . . . . . . . . . -0.5 to 3.75V
CCAUX
Supply Voltage V
. . . . . . . . . . . . . . . . . . -0.5 to 3.75V
CCJ
Output Supply Voltage V
. . . . . . . . . . . -0.5 to 3.75V
CCIO
Input or I/O Tristate Voltage Applied4 . . . . . . -0.5 to 3.75V
Storage Temperature (Ambient) . . . . . . . . . -65 to 150°C
Junction Temperature (Tj) . . . . . . . . . . . . . . . . . . +125°C
1. Stress above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (V
+ 2) volts is permitted for a duration of <20ns.
IHMAX
Recommended Operating Conditions
Symbol
1, 4, 5
Parameter
Min.
1.14
3.135
1.14
1.14
1.14
0
Max.
1.26
3.465
1.26
3.465
3.465
85
Units
V
V
V
V
V
V
Core Supply Voltage
CC
1, 3, 4, 5
Auxiliary Supply Voltage
V
CCAUX
CCPLL
PLL Supply Voltage
V
1, 2, 4
I/O Driver Supply Voltage
V
CCIO
1
Supply Voltage for IEEE 1149.1 Test Access Port
Junction Temperature, Commercial Operation
Junction Temperature, Industrial Operation
V
CCJ
t
t
°C
°C
JCOM
JIND
-40
100
SERDES External Power Supply (For LatticeECP2M Family Only)
Input Buffer Power Supply (1.2V)
1.14
1.425
1.14
1.26
1.575
1.26
V
V
V
V
V
V
V
V
V
V
CCIB
Input Buffer Power Supply (1.5V)
Output Buffer Power Supply (1.2V)
Output Buffer Power Supply (1.5V)
Termination Resistor Switching Power Supply
Receive Power Supply
CCOB
1.425
3.135
1.14
1.575
3.465
1.26
V
V
V
V
CCAUX33
6
CCRX
6
Transmit Power Supply
1.14
1.26
CCTX
6
PLL and Reference Clock Buffer Power
is set to 1.2V, they must be connected to the same power supply as V
1.14
1.26
CCP
1. If V
or V
If V
or V
is set to 3.3V, they must be con-
CCJ
CCIO
CCJ
CC.
CCIO
nected to the same power supply as V
. V and V
must be connected to the same power supply.
CCAUX CC
CCPLL
2. See recommended voltages by I/O standard in subsequent table.
3. V ramp rate must not exceed 30mV/µs during power-up when transitioning between 0V and 3.3V.
CCAUX
4. For proper power-up configuration, users must ensure that the configuration control signals such as the CFGx, INITN, PROGRAMN and
DONE pins are driven to the proper logic levels when the device powers up. The device power-up is triggered by the last of V , V
or
CC CCAUX
V
supplies that reaches its minimum valid levels. Alternatively, if the configuration control signals are pulled up by V
, the V
CCIO8
CCIO8 CCIO8
(configuration I/O bank) voltage must be powered up prior to or at the same time as the last of VCC or VCCAUX reaches its minimum levels.
5. For power-up, V must reach its valid minimum value before powering up V (LatticeECP2/M “S” version devices only).
CC
CCAUX
6. V
,V
and V
must be tied together in each quad and all quads need to be powered up.
CCRX CCTX
CCP
© 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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DS1006 DC and Switching_01.7
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