Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
SERDES and PCS (Physical Coding Sublayer)
LatticeECP2M devices feature up to 16 channels of embedded SERDES arranged in quads at the corners of the
devices. Figure 2-39 shows the position of the quad blocks in relation to the PFU array for LatticeECP2M70 and
LatticeECP2M100 devices. Table 2-15 shows the location of Quads for all the devices.
Each quad contains four dedicated SERDES (Ch0 to Ch3) for high-speed, full-duplex serial data transfer. Each
quad also has a PCS block that interfaces to the SERDES channels and contains digital logic to support an array of
popular data protocols. PCS also contains logic to the interface to FPGA core.
Figure 2-39. SERDES Quads (LatticeECP2M70/LatticeECP2M100)
ULC SERDES Quad
Ch 3 Ch 2 Ch 1 Ch 0
PCS Digital Logic
URC SERDES Quad
Ch 3 Ch 2 Ch 1 Ch 0
PCS Digital Logic
PCS Digital Logic
Ch 3 Ch 2 Ch 1 Ch 0
PCS Digital Logic
Ch 3 Ch 2 Ch 1 Ch 0
LLC SERDES Quad
LRC SERDES Quad
Table 2-15. Available SERDES Quads per LatticeECP2M Devices
Device
URC Quad
Available
Available
Available
Available
Available
ULC Quad
—
LRC Quad
—
LLC Quad
—
ECP2M20
ECP2M35
ECP2M50
ECP2M70
ECP2M100
—
—
—
—
Available
Available
Available
—
Available
Available
Available
Available
SERDES Block
A differential receiver receives the serial encoded data stream, equalizes the signal, extracts the buried clock and
de-serializes the data-stream before passing the 8- or 10-bit data to the PCS logic. The transmit channel receives
the parallel (8- or 10-bit) encoded data, serializes the data and transmits the serial bit stream through the differen-
tial buffers. There is a single transmit clock per quad. Figure 2-40 shows a single channel SERDES and its inter-
face to the PCS logic. Each SERDES receiver channel provides a recovered clock to the PCS block and to the
FPGA core logic.
2-46
LATTICE [ LATTICE SEMICONDUCTOR ]
