Architecture
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
Table 2-13. Supported Input Standards
Input Standard
Single Ended Interfaces
LVTTL
V
(Nom.)
V
1 (Nom.)
CCIO
REF
—
—
—
—
—
—
—
—
—
—
LVCMOS33
LVCMOS25
LVCMOS18
1.8
1.5
—
LVCMOS15
LVCMOS12
PCI 33
3.3
—
HSTL18 Class I, II
HSTL15 Class I
0.9
0.75
1.5
—
SSTL3 Class I, II
—
SSTL2 Class I, II
1.25
0.9
—
SSTL18 Class I, II
Differential Interfaces
Differential SSTL18 Class I, II
Differential SSTL2 Class I, II
Differential SSTL3 Class I, II
Differential HSTL15 Class I
Differential HSTL18 Class I, II
LVDS, MLVDS, LVPECL, BLVDS, RSDS
—
—
—
—
—
—
—
—
—
—
—
—
—
1
When not specified, V
can be set anywhere in the valid operating range (page 3-1).
CCIO
2-44
LATTICE [ LATTICE SEMICONDUCTOR ]
