Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)
LFE2-20E/SE
Ball
Number
Ball Number
L11
Ball/Pad Function
PB61B
Bank
4
4
4
4
4
4
-
Dual Function
BDQ60
Differential
L11
C
T
T
T13
T13
PB62A
BDQ60
R13
VCCIO
T14
R13
PB63A
BDQ60
VCCIO
T14
VCCIO4
PB62B
BDQ60
BDQ60
C
C
P13
P13
PB63B
GND
N12
M12
R15
N14
N13
N15
P15
GND
N12
GNDIO4
PB64A
4
4
8
8
8
8
8
8
8
-
VREF2_4/BDQ60
VREF1_4/BDQ60
T
M12
R15
PB64B
C
CFG2
N14
CFG1
N13
PROGRAMN
CFG0
N15
P15
PR44B
WRITEN
C
C
L12
L12
INITN
N16
GND
R14
P14
N16
PR43B
CSN
GND
R14
GNDIO8
CCLK
8
8
8
8
8
8
8
8
-
P14
PR44A
CS1N
D1
T
M13
R16
VCCIO
M16
P16
M13
R16
DONE
PR42B
C
VCCIO
M16
P16
VCCIO8
PR43A
D0/SPIFASTN
T
T
C
PR42A
D2
D3
L15
L15
PR41B
GND
L14
GND
L14
GNDIO8
PR40A
8
8
8
8
8
8
8
8
-
D6
D4
D7
D5
T
T
L16
L16
PR41A
L10
L10
PR39B
C
C
L13
L13
PR40B
VCCIO
K11
VCCIO
K11
VCCIO8
PR39A
DI/CSSPI0N
DOUT/CSON
BUSY/SISPI
T
C
T
K14
K14
PR38B
K13
K13
PR38A
GND
K15
GND
K15
GNDIO8
PR31B
3
3
3
-
RLM0_GPLLC_FB_A/RDQ34
RLM0_GPLLT_FB_A/RDQ34
C
T
VCCIO
K16
VCCIO
K16
VCCIO3
PR31A
GND
J16
GND
J16
GNDIO3
PR30B
3
3
3
RLM0_GPLLC_IN_A**/RDQ34
RLM0_GPLLT_IN_A**/RDQ34
C (LVDS)*
T (LVDS)*
J15
J15
PR30A
J14
J14
RLM0_PLLCAP
4-42
LATTICE [ LATTICE SEMICONDUCTOR ]
