Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-20E/SE Logic Signal Connections: 256 fpBGA (Cont.)
LFE2-20E/SE
Ball
Number
Ball Number
P5
Ball/Pad Function
VCCIO5
VCCIO6
VCCIO6
VCCIO7
VCCIO7
VCCIO8
GND
Bank
Dual Function
Differential
P5
5
6
6
7
7
8
-
K5
K5
M3
E3
M3
E3
G5
G5
T15
A1
T15
A1
A16
B12
B5
A16
B12
B5
GND
-
GND
-
GND
-
C8
C8
GND
-
E15
E2
E15
E2
GND
-
GND
-
H14
H8
H14
H8
GND
-
GND
-
H9
H9
GND
-
J3
J3
GND
-
J8
J8
GND
-
J9
J9
GND
-
M15
M2
P9
M15
M2
GND
-
GND
-
P9
GND
-
R12
R5
R12
R5
GND
-
GND
-
T1
T1
GND
-
T16
T16
GND
-
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
4-46
LATTICE [ LATTICE SEMICONDUCTOR ]
