Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.)
LFE2-6E/SE
LFE2-12E/SE
Ball
Number
Ball/Pad
Function
Ball/Pad
Function
Bank Dual Function
Differential
Bank Dual Function
Differential
R12
R5
GND
GND
GND
GND
-
-
-
-
GND
GND
GND
GND
-
-
-
-
T1
T16
* Supports true LVDS. Other differential signals must be emulated with external resistors.
** These dedicated input pins can be used for GPLLs or GDLLs within the respective quadrant.
Note:VCCIO and GND pads are used to determine the average DC current drawn by I/Os between GND/VCCIO connections, or between the
last GND/VCCIO in an I/O bank and the end of an I/O bank. The substrate pads listed in the Pin Table do not necessarily have a one to one
connection with a package ball or pin.
4-38
LATTICE [ LATTICE SEMICONDUCTOR ]
