Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-20E/SE Logic Signal Connections: 256 fpBGA
LFE2-20E/SE
Ball
Number
Ball Number
C3
Ball/Pad Function
PL2A
Bank
7
7
7
7
7
7
7
-
Dual Function
VREF2_7
Differential
T (LVDS)*
C (LVDS)*
C3
C2
C2
PL2B
VREF1_7
VCCIO
-
VCCIO
GND
D3
VCCIO7
GNDIO7
PL7A
D3
LDQ8
LDQ8
LDQ8
T
T (LVDS)*
C
D4
D4
PL6A
D2
D2
PL7B
GND
E4
GND
E4
GNDIO7
PL6B
7
7
7
7
7
7
7
7
7
-
LDQ8
LDQ16
LDQ16
LDQ16
C (LVDS)*
B1
B1
PL13A
PL13B
PL15A
VCCIO
PL14A
PL15B
PL14B
PL16A
GNDIO7
PL16B
PL17A
PL17B
VCCIO7
PL18A
PL18B
GNDIO7
PL19A
PL19B
PL21A
VCCIO6
PL21B
PL22A
GNDIO6
PL22B
PL27A
PL27B
VCC
T
C
T
C1
C1
F5
F5
VCCIO
F4
VCC
F4
LDQ16
LDQ16
LDQ16
LDQS16
T (LVDS)*
C
G6
G6
G4
G4
C (LVDS)*
T (LVDS)*
D1
D1
GND
E1
GND
E1
7
7
7
7
7
7
-
LDQ16
LDQ16
LDQ16
C (LVDS)*
F3
F3
T
G3
G3
C
VCCIO
F2
VCCIO
F2
LDQ16
LDQ16
T (LVDS)*
C (LVDS)*
F1
F1
GND
G2
GND
G2
7
7
6
6
6
6
-
PCLKT7_0/LDQ16
PCLKC7_0/LDQ16
PCLKT6_0/LDQ25
T
C
G1
G1
H6
H6
T (LVDS)*
VCCIO
H5
VCCIO
H5
PCLKC6_0/LDQ25
VREF2_6/LDQ25
C (LVDS)*
T
H4
H4
GND
H3
GND
H3
6
6
6
-
VREF1_6/LDQ25
C
H2
H2
LLM0_GDLLT_IN_A**/LDQ25
LLM0_GDLLC_IN_A**/LDQ25
T (LVDS)*
C (LVDS)*
H1
H1
G10
J4
G10
J4
PL28A
PL28B
LLM0_PLLCAP
PL30A
GNDIO6
6
6
6
6
-
LLM0_GDLLT_FB_A/LDQ25
LLM0_GDLLC_FB_A/LDQ25
T
J5
J5
C
J6
J6
K4
K4
LLM0_GPLLT_IN_A**/LDQ34
T (LVDS)*
GND
GND
4-39
LATTICE [ LATTICE SEMICONDUCTOR ]
