Pinout Information
LatticeECP2/M Family Data Sheet
Lattice Semiconductor
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.)
LFE2-6E/SE
LFE2-12E/SE
Ball
Number
Ball/Pad
Function
Ball/Pad
Function
Bank Dual Function
Differential
Bank
Dual Function
Differential
N14
N13
N15
P15
CFG1
PROGRAMN
CFG0
8
8
8
8
8
8
-
CFG1
PROGRAMN
CFG0
8
8
8
8
8
8
-
PR30B
INITN
WRITEN
C
C
PR30B
INITN
WRITEN
C
C
L12
N16
GND
R14
P14
PR29B
GNDIO8
CCLK
CSN
PR29B
GNDIO8
CCLK
CSN
8
8
8
8
8
8
8
8
-
8
8
8
8
8
8
8
8
-
PR30A
DONE
CS1N
D1
T
PR30A
DONE
CS1N
D1
T
M13
R16
VCCIO
M16
P16
PR28B
VCCIO8
PR29A
PR28A
PR27B
GNDIO8
PR26A
PR27A
PR25B
PR26B
VCCIO8
PR25A
PR24B
PR24A
GNDIO8
PR21B
VCCIO3
PR21A
GNDIO3
PR20B
PR20A
RLM0_PLLCAP
PR18B
PR18A
PR17B
GNDIO3
PR17A
PR16B
VCCIO3
PR16A
PR15B
PR15A
PR13B
GNDIO2
PR13A
C
PR28B
VCCIO8
PR29A
PR28A
PR27B
GNDIO8
PR26A
PR27A
PR25B
PR26B
VCCIO8
PR25A
PR24B
PR24A
GNDIO8
PR21B
VCCIO3
PR21A
GNDIO3
PR20B
PR20A
RLM0_PLLCAP
PR18B
PR18A
PR17B
GNDIO3
PR17A
PR16B
VCCIO3
PR16A
PR15B
PR15A
PR13B
GNDIO2
PR13A
C
D0/SPIFASTN
T
T
C
D0/SPIFASTN
T
T
C
D2
D3
D2
D3
L15
GND
L14
8
8
8
8
8
8
8
8
-
D6
D4
D7
D5
T
T
8
8
8
8
8
8
8
8
-
D6
D4
D7
D5
T
T
L16
L10
C
C
C
C
L13
VCCIO
K11
DI/CSSPI0N
DOUT/CSON
BUSY/SISPI
T
C
T
DI/CSSPI0N
DOUT/CSON
BUSY/SISPI
T
C
T
K14
K13
GND
K15
3
3
3
-
RLM0_GPLLC_FB_A
RLM0_GPLLT_FB_A
C
T
3
3
3
-
RLM0_GPLLC_FB_A
RLM0_GPLLT_FB_A
C
T
VCCIO
K16
GND
J16
3
3
3
3
3
3
-
RLM0_GPLLC_IN_A**
RLM0_GPLLT_IN_A**
C (LVDS)*
T (LVDS)*
3
3
3
3
3
3
-
RLM0_GPLLC_IN_A** C (LVDS)*
J15
RLM0_GPLLT_IN_A**
T (LVDS)*
J14
J13
RLM0_GDLLC_FB_A
RLM0_GDLLT_FB_A
RLM0_GDLLC_IN_A**
C
T
RLM0_GDLLC_FB_A
RLM0_GDLLT_FB_A
C
T
J12
H12
GND
H13
H15
VCCIO
H16
H11
J11
C (LVDS)*
RLM0_GDLLC_IN_A** C (LVDS)*
3
3
3
3
3
3
2
-
RLM0_GDLLT_IN_A**
VREF2_3
T (LVDS)*
C
3
3
3
3
3
3
2
-
RLM0_GDLLT_IN_A**
VREF2_3
T (LVDS)*
C
VREF1_3
PCLKC3_0
T
VREF1_3
PCLKC3_0
T
C (LVDS)*
T (LVDS)*
C
C (LVDS)*
T (LVDS)*
C
PCLKT3_0
PCLKT3_0
G16
GND
G15
PCLKC2_0/RDQ10
PCLKC2_0/RDQ10
2
PCLKT2_0/RDQ10
T
2
PCLKT2_0/RDQ10
T
4-34
LATTICE [ LATTICE SEMICONDUCTOR ]
