AN10E40 参数 Datasheet PDF下载

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AN10E40 Architecture

The AN10E40 is comprised of a 4x5 array of Configurable Analog Blocks (CABs), enmeshed in clocking, switching,

local and global routing resources. Nearly every element of the AN10E40 is programmable giving the user

tremendous flexibility in the sorts of processing circuits that can be realized.

O

CAB

O

I

CAB

CAB

CAB

CAB

I

O

CAB

O

I

CAB

CAB

CAB

CAB

I

O

CAB

O

I

CAB

CAB

CAB

CAB

I

O

CAB

O

I

X

Y

O

Z

I

X

CAB

CAB

CAB

CAB

I

Vref

O

Y

Z

I

X

Y

O

Z

I

X

Y

O

Z

I

X

Y

O

Z

Figure 1. Block Level View of the AN10E40 array

The Configuration Logic and Shift Register work together whenever chip configuration is in process. The array of

CABs is surrounded on three sides by programmable analog input/output cells, 13 in all, with two spare

uncommitted op-amps. The lower region of the chip also contains a programmable reference voltage generator.

X

Y

Z

X

Y

Z

X

Y

Z

X

Y

Z

A

Config. Logic

Configuration Data Shift Register

B

C

X

Y

Z

X

Y

Z

X

Y

Z

X

Y

Z

I