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AN10E40 参数 Datasheet PDF下载

AN10E40图片预览
型号: AN10E40
PDF下载: 下载PDF文件 查看货源
内容描述: [现场可编程模拟器件]
分类和应用:
文件页数/大小: 37 页 / 292 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
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AN10E40 Data Manual  
19  
36  
37  
38  
39  
40  
41  
IOLAY  
IOLAX  
VREFOUT  
BVDD  
BVSS  
Analog Input  
Analog Input  
Analog Output  
Power Supply  
Power Supply  
Analog Output  
Buffered Analog input  
Unbuffered Analog input  
Reference voltage  
Bandgap VDD, 5 Volts  
Bandgap VSS, 0 Volts  
VMR  
Signal ground, 2.5 Volts  
Normally left floating. Can be driven by off chip  
generator if the on chip VMR generator is  
disabled.  
42  
43  
OPAMP_VMR  
CEXT  
Signal ground, 2.5 Volts  
(usually loaded with 100nF to AVSS)  
External Reference Generator Capacitor  
(usually loaded with 10nF to AVSS)  
Buffered op-amp output  
Buffered Analog input  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
IOD5Z  
IOD5Y  
IOD5X  
IOD4Z  
IOD4Y  
IOD4X  
ESD_VDD  
ESD_VSS  
IOD3Z  
IOD3Y  
IOD3X  
IOD2Z  
IOD2Y  
IOD2X  
IOD1Z  
IOD1Y  
IOD1X  
IORAX  
IORAY  
IORAZ  
IORBZ  
IORBY  
IORBX  
CFG_VDD  
SVSS  
Analog Output  
Analog Input  
Analog Input  
Analog Output  
Analog Input  
Analog Input  
Power Supply  
Power Supply  
Analog Output  
Analog Input  
Analog Input  
Analog Output  
Analog Input  
Analog Input  
Analog Output  
Analog Input  
Analog Input  
Analog Input  
Analog Input  
Analog Output  
Analog Output  
Analog Input  
Analog Input  
Power Supply  
Power Supply  
Power Supply  
Digital Input  
Unbuffered Analog input  
Buffered op-amp output  
Buffered Analog input  
Unbuffered Analog input  
ESD Structures VDD, 5 Volts  
ESD Structures VSS, 0 Volts  
Buffered op-amp output  
Buffered Analog input  
Unbuffered Analog input  
Buffered Analog output  
Buffered Analog input  
Unbuffered Analog input  
Buffered Analog output  
Buffered Analog input  
Unbuffered Analog input  
Unbuffered Analog input  
Buffered Analog input  
Buffered Analog output  
Buffered Analog output  
Buffered Analog input  
Unbuffered Analog input  
Configuration (Digital) VDD ,5 Volts  
Substrate VSS, 0 Volts  
SVDD  
CLOCK  
Substrate VDD, 5 Volts  
System master clock  
Used by clock generator which feeds all switch  
capacitor analog circuitry.  
Unbuffered Analog input  
Buffered Analog Input  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
IORCX  
IORCY  
IORCZ  
IORDY2  
IORDZ2  
CFG_VSS  
IORDZ  
IORDY  
IORDX  
POR  
Analog Input  
Analog Input  
Analog Output  
Analog Input  
Analog Output  
Power Supply  
Analog Output  
Analog Input  
Analog Input  
Digital Input  
Buffered Analog output  
Uncommitted op-amp input  
Uncommitted op-amp output  
Configuration (Digital) VSS, 0 Volts  
Buffered Analog output  
Buffered Analog input  
Unbuffered Analog input  
Power on Reset  
Connection to VSS is typical. This input has an  
active weak pull down device (capable of sinking 100  
uA). If actively driving this pin, a pull up resistor may  
be necessary to provide additional high state current.  
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