12
DATA DATA
[7:4]
XXXX
XXXX
[3:0]
0000
0001
Micro Mode Function Register Behavior
Normal Operation – No function performed.
Reset Device – Entire device configuration memory is reset. BUSY is asserted until the reset
sequence is complete.
XXXX
0010
Load Configuration – After writing this command, a complete configuration image should be
presented to the data register in 8 bit segments, starting with the configuration header block. At
any time during the loading process, a read from the data register will return status register
contents. As complete rows including Error Check Bytes (ECB) are loaded, BUSY is temporarily
asserted while row data is transferred from the internal data shift register to the currently
addressed SRAM memory row. Once this write operation is complete, BUSY is deasserted and
additional data can be written. Each time BUSY is deasserted, the status register should be
checked for incorrect ID or row configuration data errors. Once an error is detected, NO further
write accesses to the data shift register will be accepted until the device is reset, or another load
configuration command is issued.
XXXX
XXXX
0011
0100
Reset Row – Indicates that the next data written to the data register will be a device row
address. After the address is written, the contents of that configuration memory row are reset.
BUSY is asserted after the address is written and deasserted when the operation is complete.
Load Row – Indicates that the next data written to the data register will be a device row address
followed by configuration date for that row including the terminating ECB. After the ECB is
written, BUSY will be asserted during the internal write and deasserted when the write
completes. Reading the data register returns status register contents. The status register should
be checked for row configuration data errors. Once an error has been detected, NO further write
accesses to the data register will be accepted until the device is reset or a load configuration
command is issued.
XXXX
XXXX
0101
0110
Read Row – The next data written to the data register will be interpreted as a row address. After
the row address is written, BUSY is asserted while row data is copied into the data shift register.
BUSY is deasserted when the transfer is complete. Subsequent successive reads from the data
register will return row configuration data. No ECB is returned. The row data read back is the
same order as it was written, rightmost byte first.
Read Device ID – 4 subsequent reads form the data register will return the device ID. The most
significant ID byte is read first. The value of the device ID is 13 85 02 B7.
(Factory Reserved)
-
-
0111
1XXX
XXXX
XXXX
(Factory Reserved)
1XXX
X1XX
(Factory Reserved)
Internal Oscillator Disable – Normally always enabled. If internal configuration clock is
selected, oscillator can not be disabled. Writing a 0 re-enables the oscillator.
(Factory Reserved)
XX1X
XXX1
XXXX
XXXX
Analog Enable – Powers up Analog IO Cells and CAB Op-Amps.
Figure 14. Micro Mode Function Register Behavior
DATA
Micro Mode Status Register Contents
[7:0]
(Data[7:3] are factory reserved. Their function may change without notice.)
Incorrect Device ID detected in configuration data stream.
Row configuration data error (ECB mismatch).
XXXXXXX1
XXXXXX1X
XXXXX1XX
XXXX1XXX
XXX1XXXX
XX1XXXXX
X1XXXXXX
1XXXXXXX
Busy signal asserted. Allows software handshaking if hardware wait states are not to be used.
Asserted while last internal configuration SRAM row is being written.
Test_Count_0
End_Test
Last_Byte, asserted when last configuration byte is being written.
ID_Full, asserted when the ID has been written to the device.
Figure 15. Micro Mode Status Register Contents
LATTICE [ LATTICE SEMICONDUCTOR ]
