ML145170
LANSDALE Semiconductor, Inc.
applications. An external feedback resistor of approximately
nal, except when a divide ration of 1 is selected. When 1 is
5 MΩ is required across the OSC and OSC
pins in the
selected, the OSC signal is buffered and appears at the f pin.
in
out
in
R
AC–coupled case (see Figure 8a or alternate circuit 8b).
OSC is an internal node on the device and should not be
f
V
out
N Counter Output (Pin 10)
This signal is the buffered output of the 16–stage N counter.
can be enabled or disabled via the C register (patented).
used to drive any loads (i.e. OSC
is unbuffered). However,
out
the buffered REF
is available to drive external loads.
out
f
V
The external signal level must be at least 1 V p–p; the maxi-
mum frequencies are given in the Loop Specifications table.
These maximum frequencies apply for R Counter divide ratios
as indicated in the table. For very small ratios, the maximum
frequency is limited to the divide ratio times 2 MHz. (Reason:
the phase/frequency detectors are limited to a maximum input
frequency of 2 MHz.)
The output is disabled (static low logic level) upon power up.
If unused, the output should be left disabled and unconnected
to minimize interference with external circuitry.
The f signal can be used to verify the N counter’s divide
V
ratio. This ratio extends from 40 to 65,535 and is determined
by the binary value loaded into the N register. The maximum
frequency which the phase detectors operate is 2 MHz.
If an external source is available which swings virtually
Therefore, the frequency of f must not exceed 2 MHz.
V
rail–to–rail (V
to V ), then DC coupling can be used. In
DD
SS
When activated, the f signal appears as normally low and
pulses high.
V
the DC–coupled case, no external feedback resistor is needed.
OSC must be a No Connect to avoid loading an internal
out
node on the device, as noted above. For frequencies below 1
MHz, DC coupling must be used. The R counter is a static
counter and may be operated down to DC. However, wave
shaping by a CMOS buffer may be required to ensure fast rise
LOOP PINS
f
in
Frequency Input (Pin 4)
This pin is a frequency input from the VCO. This pin feeds
the on–chip amplifier which drives the N counter. This signal
is normally sourced from an external voltage–controlled oscil-
and fall times into the OSC pin. See Figure 22.
in
Each rising edge on the OSC pin causes the R counter to
in
decrement by one.
lator (VCO), and is AC–coupled into f . A 100 pF coupling
in
REF
out
capacitor is used for measurement purposes and is the mini-
mum size recommended for applications (see Figure 7). The
frequency capability of this input is dependent on the supply
voltage as listed in the Loop Specifications table. For small
divide ratios, the maximum frequency is limited to the divide
ratio times 2 MHz. (Reason: the phase/frequency detectors are
limited to a maximum frequency of 2 MHz.)
Reference Frequency Output (Pin 3)
This output is the buffered output of the crystal–generated
reference frequency or externally provided reference source.
This output may be enabled, disabled, or scaled via bits in the
C register (see Figure 14).
REF
can be used to drive a microprocessor clock input,
thereby saving a crystal. Upon power up, the on–chip
out
For signals which swing from at least the V to V levels
IL IH
power–on–initialize circuit forces REF
ed–by–8 mode.
to the OSC divid-
listed in the Electrical Characteristics table, DC coupling
may be used. Also, for low frequency signals, (less than the
minimum frequencies shown in the Loop Specifications
table), DC coupling is a requirement. The N counter is a static
counter and may be operated down to DC. However, wave
shaping by a CMOS buffer may be required to ensure fast rise
out
in
REF
is capable of operation to 10 MHz; see the Loop
out
Specifications table. Therefore, divide values for the reference
divider are restricted to two or higher for OSC frequencies
above 10 MHz.
in
If unused, the pin should be floated and should be disabled
via the C register to minimize dynamic power consumption
and electromagnetic interference (EMI).
and fall times into the f pin. See Figure 22.
in
Each rising edge on the f pin causes the N counter to decre-
ment by 1.
in
COUNTER OUTPUT PINS
PD
out
Single–Ended Phase/Frequency Detector Output (Pin 13)
f
R
R Counter Output (Pin 9)
This is a three–state output for use as a loop error signal
when combined with an external low–pass filter. The detec-
tor’s dead zone has been eliminated. Therefore, the phase/fre-
quency detector is characterized by a linear transfer function.
The operation of the phase/frequency detector is described
below and is shown in Figure 17.
This signal is the buffered output of the 15–stage R counter.
R
f can be enabled or disabled via the C register (patented). The
output is disabled (static low logic level) upon power up. If
unused, the output should be left disabled and unconnected to
minimize interference with external circuitry.
POL bit (C7) in the C register = low (see Figure 14)
The f signal can be used to verify the R counter’s divide
R
Frequency of f > f or Phase of f Leading f : negative
V
R
V
R
ratio. This ratio extends from 5 to 32,767 and is determined by
the binary value loaded into the R register. Also, direct access
to the phase detector via the OSC pin is allowed by choosing
a divide value of 1 (see Figure 15). The maximum frequency
which the phase detectors operate is 2 MHz. Therefore, the fre-
quency of f must not exceed 2 MHz.
pulses from high impedance
Frequency of f < f or Phase of f Lagging f : positive
V
R
V
R
in
pulses from high impedance
Frequency and Phase of f = f ; essentially high–impedance
V
R
state; voltage at pin determined by loop filter
POL bit (C7) = high
R
When activated, the f signal appears as normally low and
R
pulses high. The pulse width is 4.5 cycles of the OSC pin sig-
in
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