ML145170
LANSDALE Semiconductor, Inc.
Figure 14. C Register Access and Format (8 Clock Cycles are Used)
*At this point, the new byte is transferred to the C register and stored. No other registers
are affected.
C7–POL: Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts
PD
and interchanges the φ funtion with φ as depicted in Figure 17. Also see the phase
out
R V
detector output pin description for more information. This bit is cleared low at power up.
C6–PDA/B: Selects which phase/frequency detector is to be used. When set high, enables the output of
phase/frequency detector A (PD ) and disables phase/frequency detector B by forcing φ
out
R
and φ to the static high state. When cleared low, phase/frequency detector B is enabled (φ
V
R
and φ ) and phase/frequency detector A is disabled with PD
forced to the high–impedance
out
V
state. This bit is cleared low at power up.
C5–LDE: Enables the lock detector output when set high. When the bit is cleared low, the LD output is
forced to a static low level. This bit is cleared low at power up.
C4–C2, OSC2–OSC0: Reference output controls which determine the REF
characteristics as shown below. Upon
out
power up, the bits are initialized such that OSC /8 is selected.
in
C4
0
C3
0
C2
0
REF
Frequency
out
DC (Static Low)
OSC
0
0
1
in
0
1
0
OSC /2
in
0
1
1
OSC /4
in
1
0
0
OSC /8 (POR Default)
in
1
0
1
OSC /16
in
1
1
0
OSC /8
in
1
1
1
OSC /16
in
C1–f E:
Enables the f output when set high. When cleared low, the f output is forced to a static low
level. The bit is cleared low upon power up.
V
V
V
C0–f E: Enables the f output when set high. When cleared low, the f output is forced to a static low
R
R
R
level. The bit is cleared low upon power up.
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