ML145170
LANSDALE Semiconductor, Inc.
Frequency of f > f or Phase of f Leading f : positive
tially high, φ = negative pulses
V
V
R
V
R
pulses from high impedance
Frequency of f < f or Phase of f Lagging f : negative
Frequency and Phase of f = f : φ and φ remain essen-
V R V R
tially high, except for a small minimum time period when both
pulse low in phase
These outputs can be enabled, disabled, and interchanged via
the C register (patented)
V
R
V
R
pulses from high impedance
Frequency and Phase of f = f : essentially high–impedance
V
R
state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the C
LD
register. If desired, PD
state by utilization of the disable feature in the C register
(patented).
can be forced to the high–impedance
out
Lock Detector Output (Pin 11)
This output is essentially at a high level with narrow
low–going pulses when the loop is locked (f and f of the
same phase and frequency). The output pulses low when f
R
V
φ and φ
R
V
V
Double–Ended Phase/Frequency Detector Outputs (Pins 14,
and f are out of phase or different frequencies (See Figure
R
15)
17).
These outputs can be combined externally to generate a loop
error signal. Through use of a Motorola patented technique,
the detector’s dead zone has been eliminated. Therefore, the
phase/frequency detector is characterized by a linear transfer
function. The operation of the phase/frequency detector is
described below and is shown in Figure 17.
This output can be enabled and disabled via the C register
(patented). Upon power up, on–chip initialization circuitry dis-
ables LD to a static low logic level to prevent a false “lock”
signal. If unused, LD should be disabled and left open.
POWER SUPPLY
V
DD
POL bit (C7) in the C register = low (see Figure 14)
Most Positive Supply Potential (Pin 16)
Frequency of f > f or Phase of f Leading f : φ = neg-
V
R
V
R
V
ative pulses, φ = essentially high
R
This pin may range from 2.7 to 5.5 V with respect to V
.
SS
Frequency of f < f or Phase of f Lagging f : φ
=
V
R
V
R
V
For optimum performance, V
should be bypassed to V
DD SS
essentially high, φR = negative pulses
Frequency and Phase of f = f : φ and φ remain essen-
using low–inductance capacitor(s) mounted very close to the
device. Lead lengths on the capacitor(s) should be minimized.
(The very fast switching speed of the device causes current
spikes on the power leads.)
V
R
V
R
tially high, except for a small minimum time period when both
pulse low in phase
POL bit (C7) = high
V
SS
Frequency of f > f or Phase of f Leading f : φ = nega-
V
V
R
V
R
R
Most Negative Supply Potential (Pin 12)
tive pulses, φ = essentially high
This pin is usually ground. For measurement purposes, the
Frequency of f < f or Phase of f Lagging f : φ = essen-
V
R
V
R
R
V
pin is tied to a ground plane.
SS
Figure 13. Reset Sequence
NOTE: This initialization sequence is usually not necessary because the on–chip power–on reset circuit performs the initialization
function. However, this initialization sequence must be used immediately after power up if control of the CLK pin is not
possible. That is, if CLK (Pin 7) toggles or floats upon power up, use the above sequence to reset the device.
Also, use this sequence if power is momentarily interrupted such thhat the supply voltage to the device is reduced to below
2.7 V, but not down to at least 1 V (for example, the supply drops down to 2 V). This is necessary because the on–chip
power–on reset is only activated when the supply ramps up from a voltage below approximately 1.0 V.
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