ML145170
LANSDALE Semiconductor, Inc.
Figure 16. N Register Access and Format (16 Clock Cycles Are Used)
⋅
⋅
⋅
⋅
⋅
⋅
⋅ ⋅
⋅ ⋅
⋅ ⋅
÷
÷
÷
÷
⋅
⋅
⋅
⋅
⋅
⋅
⋅ ⋅
⋅ ⋅
⋅ ⋅
÷
÷
*At this point, the two new bytes are transferred to the N register and stored. No other registers are affected. In addition, the N and
R counters are jam–loaded and begin counting down together.
Figure 17. Phase/Frequency Detectors and Lock Detector Output Waveform
÷
÷
φ
φ
NOTE: The PD generates error pulses during out–of–lock conditions. When locked in phase and frequency, the output is high impedance and
out
the voltage at that pin is determined by the low–pass filter capacitor. PD , φ and φ are shown with the polarity bit (POL) - low;
out
R
V
see Figure 14 for POL.
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