IS43R16320B
IC43R16320B
512 Mb Double Data Rate Synchronous DRAM
PRELIMINARY INFORMATION
JUNE
2008
Features
Specifications
•
Density: 512M bits
•
Organization
⎯
8M words
×
16 bits
×
4 banks
•
Package: 66-pin plastic TSOP (II)
⎯
Lead-free (RoHS compliant)
•
Power supply:
⎯
DDR400:
VDD, VDDQ
=
2.6V
±
0.1V
⎯
DDR333, 266: VDD, VDDQ
=
2.5V
±
0.2V
•
Data rate: 400Mbps/333Mbps/266Mbps (max.)
•
Four internal banks for concurrent operation
•
Interface: SSTL_2
•
Burst lengths (BL): 2, 4, 8
•
Burst type (BT):
⎯
Sequential (2, 4, 8)
⎯
Interleave (2, 4, 8)
•
/CAS Latency (CL): 2, 2.5, 3
•
Precharge: auto precharge option for each burst
access
•
Driver strength: normal/weak
•
Refresh: auto-refresh, self-refresh
•
Refresh cycles: 8192 cycles/64ms
⎯
Average refresh period: 7.8μs
•
Operating ambient temperature range
⎯
TA = 0°C to +70°C
•
Double-data-rate architecture; two data transfers per
clock cycle
•
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
•
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
•
Data inputs, outputs, and DM are synchronized with
DQS
•
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00B
06/11/08
1
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
