initiatingꢀtheꢀsubsequentꢀoperation.
Violatingꢀeitherꢀofꢀtheseꢀ
IS42S16400F
IC42S16400F
REGISTER DEFINITION
Mode Register
Theꢀmodeꢀregisterꢀisꢀusedꢀtoꢀdefineꢀtheꢀspecificꢀmodeꢀ
ofꢀoperationꢀofꢀtheꢀSDRAM.ꢀThisꢀdefinitionꢀincludesꢀtheꢀ
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
MODEꢀREGISTERꢀDEFINITION.ꢀ
Mode register bits M0-M2 specify the burst length, M3
specifiesthetypeofburst(sequentialorinterleaved), M4-M6
specifyꢀtheꢀCASꢀlatency,ꢀM7ꢀandꢀM8ꢀspecifyꢀtheꢀoperatingꢀ
mode,ꢀM9ꢀspecifiesꢀtheꢀWRITEꢀburstꢀmode,ꢀandꢀM10ꢀandꢀ
M11 are reserved for future use.
Theꢀmodeꢀregisterꢀmustꢀbeꢀloadedꢀwhenꢀallꢀbanksꢀareꢀ
idle, and the controller must wait the specified time before
TheꢀmodeꢀregisterꢀisꢀprogrammedꢀviaꢀtheꢀLOADꢀMODEꢀ
REGISTERꢀcommandꢀandꢀwillꢀretainꢀtheꢀstoredꢀinformationꢀ
until it is programmed again or the device loses power.
requirements will result in unspecified operation.
MODE REGISTER DEFINITION
Address Bus
A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Mode Register (Mx)
Reserved(1)
Burst Length
M2 M1 M0
M3=0
M3=1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
Burst Type
M3
Type
0
1
Sequential
Interleaved
Latency Mode
M6 M5 M4
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Operating Mode
M8 M7 M6-M0 Mode
0
—
0
—
Defined Standard Operation
All Other States Reserved
—
Write Burst Mode
M9
0
Mode
Programmed Burst Length
Single Location Access
1. To ensure compatibility with future devices,
should program M11, M10 = "0, 0"
1
16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
03/19/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
