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IC42S16400F-6TL 参数 Datasheet PDF下载

IC42S16400F-6TL图片预览
型号: IC42S16400F-6TL
PDF下载: 下载PDF文件 查看货源
内容描述: 1梅格位×16位× 4银行( 64兆位)同步动态RAM [1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM]
分类和应用: 存储内存集成电路光电二极管动态存储器时钟
文件页数/大小: 55 页 / 822 K
品牌: ISSI [ INTEGRATED SILICON SOLUTION, INC ]
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IS42S16400F  
IC42S16400F  
CAS Latency  
Operating Mode  
TheCASlatencyisthedelay,inclockcycles,betweenꢀ  
the registrationofaREADcommandandtheavailabilityofꢀ  
theꢀfirstꢀpieceꢀofꢀoutputꢀdata.ꢀTheꢀlatencyꢀcanꢀbeꢀsetꢀtoꢀtwoꢀorꢀ  
three clocks.  
ThenormaloperatingmodeisselectedbysettingM7andM8ꢀ  
toꢀzero;ꢀtheꢀotherꢀcombinationsꢀofꢀvaluesꢀforꢀM7ꢀandꢀM8ꢀareꢀ  
reservedꢀforꢀfutureꢀuseꢀand/orꢀtestꢀmodes.ꢀTheꢀprogrammedꢀ  
burstꢀlengthꢀappliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts.  
IfꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀclockꢀedgeꢀn,ꢀandꢀ  
the latency is m clocks, the data will be available by clock  
edge n + m.ꢀTheꢀDQsꢀwillꢀstartꢀdrivingꢀasꢀaꢀresultꢀofꢀtheꢀ  
clock edge one cycle earlier (n + m - 1), and provided that  
the relevant access times are met, the data will be valid by  
clock edge n + m.ꢀForꢀexample,ꢀassumingꢀthatꢀtheꢀclockꢀ  
cycle time is such that all relevant access times are met,  
ifꢀaꢀREADꢀcommandꢀisꢀregisteredꢀatꢀT0ꢀandꢀtheꢀlatencyꢀ  
isprogrammedtotwoclocks,theDQswillstartdrivingꢀ  
afterT1ꢀandꢀtheꢀdataꢀwillꢀbeꢀvalidꢀbyꢀT2,ꢀasꢀshownꢀinꢀCASꢀ  
Latencyꢀdiagrams.TheꢀAllowable Operating Frequency  
table indicates the operating frequencies at which each  
CAS latency setting can be used.  
Testꢀmodesꢀandꢀreservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀbe-  
cause unknown operation or incompatibility with future  
versions may result.  
Write Burst Mode  
When M9 = 0, the burst length programmed via M0-M2  
appliesꢀtoꢀbothꢀREADꢀandꢀWRITEꢀbursts;ꢀwhenꢀM9ꢀ=ꢀ1,ꢀ  
theꢀprogrammedꢀburstꢀlengthꢀappliesꢀtoꢀREADꢀbursts,ꢀbutꢀ  
write accesses are single-location (nonburst) accesses.  
CAS Latency  
Allowable Operating Frequency (MHz)  
Speed  
CAS Latency = 2  
CAS Latency = 3  
Reservedꢀstatesꢀshouldꢀnotꢀbeꢀusedꢀasꢀunknownꢀoperationꢀ  
or incompatibility with future versions may result.  
5
6
7
133  
133  
133  
200  
166  
143  
CAS Latency  
T0  
T1  
T2  
T3  
CLK  
READ  
NOP  
NOP  
COMMAND  
DQ  
t
AC  
D
OUT  
OH  
t
LZ  
t
CAS Latency - 2  
T0  
T1  
T2  
T3  
T4  
CLK  
READ  
NOP  
NOP  
NOP  
COMMAND  
DQ  
t
AC  
D
OUT  
OH  
t
LZ  
t
CAS Latency - 3  
DON'T CARE  
UNDEFINED  
18  
Integrated Silicon Solution, Inc. — www.issi.com  
Rev. A  
03/19/08  
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