IS42S16400F
IC42S16400F
AC ELECTRICAL CHARACTERISTICS (1,2,3)
-6
-7
-5
Symbol Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
tc k 3ꢀ
tc k 2
ClockꢀCycleꢀTimeꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
6ꢀ
7.5ꢀ
—ꢀ
—ꢀ
7ꢀ
7.5ꢀ
—ꢀ
—ꢀ
5ꢀ
7.5ꢀ
—ꢀ
—ꢀ
ns
ns
ta c 3ꢀ
ta c 2
AccessꢀTimeꢀFromꢀCLK(4,6)
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
5ꢀ
6ꢀ
—ꢀ
—ꢀ
5.4ꢀ
6ꢀ
—ꢀ
—ꢀ
5ꢀ
6ꢀ
ns
ns
tc h iꢀ
tc l ꢀ
CLKꢀHIGHꢀLevelꢀWidthꢀ
CLKꢀLOWꢀLevelꢀWidthꢀ
OutputꢀDataꢀHoldꢀTime(6)
ꢀ
ꢀ
2ꢀ
2ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
2ꢀ
2ꢀ
—ꢀ
—ꢀ
ns
ns
to h 3ꢀ
to h 2
CASꢀLatencyꢀ=ꢀ3ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
2.7ꢀ
3ꢀ
—ꢀ
—ꢀ
2.5ꢀ
2.5ꢀ
—ꢀ
—ꢀ
ns
ns
tl z ꢀ
OutputꢀLOWꢀImpedanceꢀTimeꢀ
OutputꢀHIGHꢀImpedanceꢀTime(5)
ꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
0ꢀ
—ꢀ
ns
th z 3ꢀ
th z 2
CASꢀLatencyꢀ=ꢀ3ꢀ
CASꢀLatencyꢀ=ꢀ2ꢀ
—ꢀ
—ꢀ
5ꢀ
6ꢀ
—ꢀ
—ꢀ
5.4ꢀ
6ꢀ
—ꢀ
—ꢀ
5ꢀ
6ꢀ
ns
ns
tD s ꢀ
InputꢀDataꢀSetupꢀTimeꢀ
InputꢀDataꢀHoldꢀTimeꢀ
AddressꢀSetupꢀTimeꢀ
AddressꢀHoldꢀTimeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
—ꢀ
—ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
—ꢀ
—ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
1.5ꢀ
0.8ꢀ
—ꢀ
—ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tD h ꢀ
ta s ꢀ
—ꢀ
—ꢀ
—ꢀ
ta h ꢀ
—ꢀ
—ꢀ
—ꢀ
tc k s ꢀ
tc k h ꢀ
tc k a ꢀ
tc s ꢀ
CKEꢀSetupꢀTimeꢀ
—ꢀ
—ꢀ
—ꢀ
CKEꢀHoldꢀTimeꢀ
—ꢀ
—ꢀ
—ꢀ
CKEꢀtoꢀCLKꢀRecoveryꢀDelayꢀTimeꢀ
1CLK+3
1.5ꢀ
0.8ꢀ
60ꢀ
—
1CLK+3
2.0ꢀ
1ꢀ
—
1CLK+3ꢀ
1.5ꢀ
0.8ꢀ
55ꢀ
—
CommandꢀSetupꢀTimeꢀ(CS, RAS, CAS, WE,ꢀDQM)ꢀ ꢀ
—ꢀ
—ꢀ
—ꢀ
tc h ꢀ
CommandꢀHoldꢀTimeꢀ(CS, RAS, CAS, WE,ꢀDQM)ꢀ
CommandꢀPeriodꢀ(REFꢀtoꢀREFꢀ/ꢀACTꢀtoꢀACT)ꢀ
CommandꢀPeriodꢀ(ACTꢀtoꢀPRE)ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
1ꢀ
tr c ꢀ
—ꢀ
63ꢀ
—ꢀ
—ꢀ
tr a s ꢀ
tr p ꢀ
42ꢀ
100,000
—ꢀ
42
100,000
—ꢀ
42
100,000
—ꢀ
CommandꢀPeriodꢀ(PREꢀtoꢀACT)ꢀ
18ꢀ
20ꢀ
15ꢀ
tr c D ꢀ
tr r D ꢀ
ActiveꢀCommandꢀToꢀReadꢀ/ꢀWriteꢀCommandꢀDelayꢀTimeꢀ
CommandꢀPeriodꢀ(ACTꢀ[0]ꢀtoꢀACT[1])ꢀ
18ꢀ
—ꢀ
20ꢀ
—ꢀ
15ꢀ
—ꢀ
ꢀ
12ꢀ
—ꢀ
14ꢀ
—ꢀ
10ꢀ
—ꢀ
tD p l orꢀ
tw r ꢀ
InputꢀDataꢀToꢀPrechargeꢀ
CommandꢀDelayꢀtime
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLKꢀ
—ꢀ
2CLKꢀ
—ꢀ
2CLKꢀ
—ꢀ
CAS Latencyꢀ=ꢀ2ꢀ
CASꢀLatencyꢀ=ꢀ3ꢀ
2CLKꢀ
—ꢀ
2CLKꢀ
—ꢀ
2CLKꢀ
—ꢀ
ns
tD a l ꢀ
InputꢀDataꢀToꢀActiveꢀ/ꢀRefreshꢀ
2CLK+tr p
—
2CLK+tr p
—
2CLK+tr p
—
ns
ꢀ ꢀ ꢀ
CommandꢀDelayꢀtimeꢀ(DuringꢀAuto-Precharge)
CAS Latencyꢀ=ꢀ2ꢀ
2CLK+tr p
—
2CLK+tr p
—
2CLK+tr p
—
ns
ns
ttꢀ
TransitionꢀTimeꢀ
ꢀ
ꢀ
1ꢀ
10ꢀ
64ꢀ
1ꢀ
10ꢀ
64ꢀ
1ꢀ
10ꢀ
64ꢀ
tr e f ꢀ
RefreshꢀCycleꢀTimeꢀ(4096)ꢀ
—ꢀ
—ꢀ
—ꢀ
ms
Notes:
1.ꢀ Whenꢀpowerꢀisꢀfirstꢀapplied,ꢀmemoryꢀoperationꢀshouldꢀbeꢀstartedꢀ200ꢀµsꢀafterꢀVD D ꢀandꢀVD D q reach their stipulated voltages. Also
noteꢀthatꢀtheꢀpower-onꢀsequenceꢀmustꢀbeꢀexecutedꢀbeforeꢀstartingꢀmemoryꢀoperation.
2. measured with tt = 1 ns.
3.ꢀ Theꢀreferenceꢀlevelꢀisꢀ1.4ꢀVꢀwhenꢀmeasuringꢀinputꢀsignalꢀtiming.ꢀRiseꢀandꢀfallꢀtimesꢀareꢀmeasuredꢀbetweenꢀVih (min.)ꢀandꢀVil
(max.).
4.ꢀ Accessꢀtimeꢀisꢀmeasuredꢀatꢀ1.4Vꢀwithꢀtheꢀloadꢀshownꢀinꢀtheꢀfigureꢀbelow.
5.ꢀ Theꢀtimeꢀth z (max.)ꢀisꢀdefinedꢀasꢀtheꢀtimeꢀrequiredꢀforꢀtheꢀoutputꢀvoltageꢀtoꢀtransitionꢀbyꢀ±ꢀ200ꢀmVꢀfromꢀVo h (min.)ꢀorꢀVo l ꢀ(max.)ꢀ
when the output is in the high impedance state.
6. If clock rising time is longer than 1ns, tr/2 - 0.5ns should be added to the parameter.
Integrated Silicon Solution, Inc. — www.issi.com
13
Rev. A
03/19/08
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
