IS66WVE4M16ALL
Advanced Information
Table 9 . Asynchronous WRITE Cycle Timing Requirements
-70
Symbol
Parameter
Address setup Time
Unit
Notes
Min
0
Max
tAS
tAW
tBW
tCPH
tCW
tDH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to end of write
Byte select to end of write
CE# HIGH time during write
Chip enable to end of Write
Data hold from write time
Data write setup time
70
70
5
70
0
tDW
tLZ
23
10
5
Chip enable to Low-Z output
End write to Low-Z output
Write cycle time
1
1
tOW
tWC
tWHZ
tWP
tWPH
tWR
70
Write to High-Z output
Write pulse width
8
2
3
46
10
0
Write pulse width HIGH
Write recovery time
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The
Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
3. WE# LOW must be limited to tCEM (8us)
21
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Rev.00C | March 2010
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
