IS66WVE4M16ALL
Advanced Information
AC Characteristics
Table 8 . Asynchronous READ Cycle Timing Requirements
-70
Symbol
Parameter
Address Acess Time
Unit
Notes
Min
Max
70
20
70
8
tAA
tAPA
tBA
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page access Time
LB# /UB# access Time
tBHZ
tBLZ
tCEM
tCO
LB#/UB# disable to High-Z output
LB#/UB# enable to Low-Z output
Maximum CE# pulse width
Chip select access time
1
2
3
10
8
70
8
tHZ
Chip disable to High-Z output
Chip enable to Low-Z output
Output enable to valid output
Output hold from address change
Output disable to High-Z output
Output enable to Low-Z output
Page cycle time
1
2
tLZ
10
5
tOE
20
8
tOH
tOHZ
tOLZ
tPC
1
2
3
20
70
tRC
Read cycle time
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The High-Z timings
measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The Low-Z timings
measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or VOL.
3. Page mode enable only.
20
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Rev.00C | March 2010
ISSI [ INTEGRATED SILICON SOLUTION, INC ]
