X9428
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2
0
A0
A
C
K
I3 I2
I1 I0 R1 R0
0
0
A
C
K
0
0
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
Figure 5. Increment/Decrement Instruction Sequence
SCL
SDA
X
X
S
T
A
R
T
0
1
0
1
A3 A2
0
A0
A
C
K
I3 I2
I1 I0 R1 R0
0
0
A
C
K
I
I
D
E
C
1
S
T
I
D
N
C
1
N
C
2
N
C
n
E
C
n
O
P
Figure 6. Increment/Decrement Timing Limits
INC/DEC
CMD
Issued
t
WRID
SCL
SDA
Voltage Out
V
/R
W
W
FN8197.1
April 26, 2006
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