X9428
Figure 7. Acknowledge Response from Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
START
Acknowledge
Figure 8. Detailed Potentiometer Block Diagram
Serial Data Path
Serial
Bus
Input
V /R
H H
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
6
Parallel
Bus
Input
e
r
Wiper
D
e
c
o
d
e
Register 3
Counter
Register
(WCR)
INC/DEC
Logic
If WCR = 00[H] then V /R = V /R
W
W
L
L
UP/DN
UP/DN
If WCR = 3F[H] then V /R = V /R
H
W
W
H
V /R
Modified SCL
L
L
CLK
V
/R
W
W
FN8197.1
April 26, 2006
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