ISL88731C
and R are internal divider resistors that set the DC
Compensation Break Frequency Equations
4
output voltage. For a 3-cell battery, R = 500kΩ and
3
1
R = 100kΩ. The following equations relate the
-----------------------------------------------------------------------
F
F
F
=
4
(EQ. 23)
ZERO1
ZERO2
(2π ⋅ C
⋅ R
)
VCOMP
VCOMP
compensation network’s poles, zeros and gain to the
components in Figure 25. Figure 27 shows an asymptotic
Bode plot of the DC/DC converter’s gain vs. frequency. It
is strongly recommended that FZERO1 is approximately
30% of FLC and FZERO2 is approximately 70% of FLC.
R
R
4
⎛
⎞
⎛
⎜
⎝
⎞
⎟
⎠
gm1
5
VCOMP
⎛
⎝
⎞
⎠
-----------------------------------
--------------------
------------
=
⋅
⋅
⎜
⎝
⎟
⎠
2π ⋅ RS2 ⋅ C
R
+ R
3
(EQ. 24)
(EQ. 25)
o
4
1
-------------------------------
=
LC
(2π L ⋅ C )
o
NO BATTERY
1
------------------------------------------
=
F
F
(EQ. 26)
(EQ. 27)
(EQ. 28)
FILTER
(2π ⋅ R ⋅ C
)
F2
F2
R
BATTERY
= 200mΩ
1
----------------------------------------
=
POLE1
(2π ⋅ RS2 ⋅ C )
o
R
BATTERY
= 50mΩ
1
-------------------------------------------
F
=
ESR
(2π ⋅ C ⋅ R
)
ESR
o
Choose R
equal or lower than the value calculated
from Equation 29.
VCOMP
R
+ R
4
R
4
⎛
⎜
⎝
⎞
⎟
⎠
5
gm1
3
⎛
⎝
⎞
⎠
-----------
--------------------
R
= (0.7 ⋅ F ) ⋅ (2π ⋅ C ⋅ RS2) ⋅
⋅
VCOMP
LC
o
(EQ. 29)
Next, choose C
calculated from Equation 30.
equal or higher than the value
VCOMP
1
(EQ. 30)
--------------------------------------------------------------------------
C
=
VCOMP
FREQUENCY (Hz)
(0.3 ⋅ F ) ⋅ (2π ⋅ R
)
VCOMP
LC
FIGURE 26. FREQUENCY RESPONSE OF THE LC OUTPUT
FILTER
PCB Layout Considerations
Power and Signal Layers Placement on the
PCB
60
COMPENSATOR
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal
layers on the opposite side of the board. As an example,
layer arrangement on a 4-layer board is shown in the
following:
MODULATOR
40
20
LOOP
F
LC
F
POLE1
1. Top Layer: signal lines, or half board for signal lines
and the other half board for power lines
0
F
FILTER
2. Signal Ground
-20
-40
-60
3. Power Layers: Power Ground
F
ZERO1
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
F
ZERO2
F
ESR
Separate the power voltage and current flowing path
from the control and logic level signal path. The
controller IC will stay on the signal layer, which is isolated
by the signal ground to the power signal traces.
0.1k
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 27. ASYMPTOTIC BODE PLOT OF THE VOLTAGE
CONTROL LOOP GAIN
Component Placement
The power MOSFET should be close to the IC so that the
gate drive signal, the LGATE, UGATE, PHASE, and BOOT,
traces can be short.
Place the components in such a way that the area under
the IC has less noise traces with high dv/dt and di/dt,
such as gate signals and phase node signals.
FN6978.0
March 8, 2010
22
INTERSIL [ Intersil ]
