ISL88731C
current is below the limit set by ACLIM). The voltage
60
40
20
0
error amplifier (GMV) discharges the cap on VCOMP to
limit the output voltage. The current to the battery
decreases as the cells charge to the fixed voltage and the
voltage across the internal battery resistance decreases.
As battery current decreases the 2 current error
amplifiers (GMI and GMS) output their maximum current
and charge the capacitor on ICOMP to its maximum
voltage (limited to 0.3V above VCOMP). With high
voltage on ICOMP, the minimum voltage buffer output
equals the voltage on VCOMP.
F
ZERO
F
POLE1
-20
-40
-60
F
FILTER
The voltage control loop is shown in Figure 25.
COMPENSATOR
MODULATOR
LOOP
L
PHASE
F
POLE2
11
0.01k
0.1k
1k
10k
100k
1M
RFET_RDSON
RL_DCR
FREQUENCY (Hz)
FIGURE 23. CHARGE CURRENT LOOP BODE PLOTS
CA2
RF2
+
CSOP
CSON
0.25
+
S
Σ
-
20x
CF2
RS2
-
DCIN
R3
VCOMP
L
RBAT
PHASE
-
GMV
+
RS1
CO
RESR
11
R4
RFET_RDSON
RL_DCR
RF1
CVCOMP
RVCOMP
DACV
CF1
CA2
RF2
CSOP
CSON
+
0.25
+
20X
-
S
Σ
-
CF2
RS2
FIGURE 25. VOLTAGE CONTROL LOOP
Output LC Filter Transfer Functions
CSSN
CSSP
-
+
20
CO
RBAT
CA1
The gain from the phase node to the system output and
battery depend entirely on external components. Typical
output LC filter response is shown in Figure 26. Transfer
function ALC(s) is shown in Equation 22:
s
RESR
-
GMS
+
DACS
ICOMP
CICOMP
⎛
⎝
⎞
⎠
---------------
ESR
1 –
ω
----------------------------------------------------------
A
=
LC
2
⎛
⎜
⎝
⎞
s
ω
s
FIGURE 24. ADAPTER CURRENT LIMIT LOOP
----------- ------------------------
DP
+
+ 1
⎟
⎠
(ω ⋅ Q)
LC
The loop response equations, bode plots and the
selection of CICOMP are the same as the charge current
control loop with loop gain reduced by the duty cycle and
the ratio of R /R . In other words, if R = R and
S1 S2 S1 S2
the duty cycle D = 50%, the loop gain will be 6dB lower
than the loop gain in Figure 24. This gives lower
crossover frequency and higher phase margin in this
mode. If R /R = 2 and the duty cycle is 50% then the
adapter current loop gain will be identical to the gain in
Figure 24.
1
1
L
C
o
--------------------------------
ESR
ω
=
-----------------------
=
ω
Q = R
⋅
------
ESR
LC
(R
⋅ C )
o
o
( L ⋅ C )
o
(EQ. 22)
The resistance RO is a combination of MOSFET r
inductor DCR, R
SENSE
battery (normally between 50mΩ and 200mΩ) The worst
case for voltage mode control is when the battery is
absent. This results in the highest Q of the LC filter and
the lowest phase margin.
,
DS(ON)
and the internal resistance of the
S1 S2
A filter should be added between RS1 and CSIP and CSIN
to reduce switching noise. The filter roll off frequency
should be between the cross over frequency and the
switching frequency (~100kHz).
The compensation network consists of the voltage error
amplifier GMV and the compensation network R
,
VCOMP
C
which give the loop very high DC gain, a very
VCOMP
Voltage Control Loop
low frequency pole and a zero at F
. Inductor
ZERO1
current information is added to the feedback to create a
second zero F . The low pass filter R , C
When the battery is charged to the voltage set by
ChargeVoltage register, the voltage error amplifier (GMV)
takes control of the output (assuming that the adapter
ZERO2 F2 F2
between R and ISL88731C add a pole at F
. R
S2 FILTER
3
FN6978.0
March 8, 2010
21
INTERSIL [ Intersil ]
