HI-7152
ADDRESS BUS
ADDRESS
DECODER
ADDRESS
DECODER
DG
BUS
HBE
CS
ANALOG
INPUTS
WR
V
IN
CS
RD
D
PROGRAMMBLE
GAIN AMP
S1
S2
S3
S4
S5
S6
S7
S8
V+
V-
DG
V
REF
AG
V+
+2.56V
WR
HI-7152
ADC
(SLOW MEMORY MODE)
MICROPROCESSOR
DG528
MUX
SIGNAL
GROUND
SMOD
HOLD
BUSY
CLK
V+
+5V
-5V
RS
SYSTEM
RESET
V-
DG
600kHz
CLOCK
D0-D2, EN
SET
GND
V+
D0-D7
D8-D9, OVR
8-BIT DATA BUS
FIGURE 9. MULTI-CHANNEL DATA ACQUISITION SYSTEM WITH PROGRAMMABLE GAIN
V+
BUS
HBE
SMODE
TO PARALLEL
DATA BUS
D0-D3
64 x 4-BIT
FIFO
V
IN
ANALOG INPUT
D8-D9, OVR
V
REF
AG
V+
+2.56V
SET
HI-7152
ADC
V+
SIGNAL
GROUND
CLK
D4-D7
64 x 4-BIT
FIFO
COMPOSITE
OUTPUT
READY
600kHz
HOLD
+5V
-5V
V-
BUSY
DG
RD
WR
CS
D8-D9, OVR
64 x 4-BIT
FIFO
GND
SHIFT IN
SHIFT
OUT
DG
FIGURE 10. DMA/FIFO DATA ACQUISITION SYSTEM
6-16
INTERSIL [ Intersil ]
