BBT3821
2
FIGURE 24. I C OPERATION TIMING
TSCLH_L
TSCL_DAV
TSDA_CLV
TSDA_CLV
SCL
SDA
Start
Data
Data
Stop
Applications Information
CX4/LX4/XAUI Re-timer Setup
For certain non-10GBASE-X uses, or for debug and problem
analysis purposes, and in particular for certain BIST testing,
it may be advantageous to change some of the settings. To
achieve this, the relevant (PMA/D and/or PHY XS) XAUI_EN
bits must be turned off (to ‘0’), since otherwise they will
override many of the other registers’ bits (see Table 65). For
instance, if it desirable to change Byte Alignment to a
simpler algorithm than the IEEE-defined one (if, for example,
only three of the four lanes are working), the
PCS_SYNC_EN bit(s) (Table 63 and/or Table 80) may be
turned off, and (with the respective XAUI_EN bit off), byte
(code group) alignment on the working lanes will now
function. Similarly, setting the A_ALIGN_DIS bit in the
PCS/PHY XS Control Register 2 ([3,4].C000’h) will cause
lane alignment to occur on IDLE to non-IDLE transitions
across all four lanes, instead of lane alignment on ||A||
(K28.3) character columns when this bit is set to a zero. The
internal (pseudo-XGMII) ERROR character can be set to a
value other than 1FE’h by writing the value (without the K bit)
to register 3.C002’h or 4.C002’h. Similarly, the internal
(pseudo-XGMII) IDLE character may be changed using
registers 3.C003’h and/or 4.C003’h. The pseudo-random
XAUI/CX4/LX4 IDLE /A/K/R/ generator can be disabled by
clearing the AKR_SM_EN bit in register 3.C001’h (PCS) or
4.C001’h (PHY XS). To disallow complete regeneration of
the Inter Packet Gap (IPG), it would be desirable to clear the
TRANS_EN bit in register 3.C001’h/4.C001’h.
This section discusses the setup for the BBT3821 to be used
as a XAUI/CX4/LX4 Retimer. The various descriptions and
comments further assume that the device is initially
configured in the default condition (i.e. exactly as found after
a hardware reset). The BIST_ENA pin should be pulled
LOW (to GND); the pin has an internal pulldown to this
value. The LX4_MODE select pin should be tied to the
appropriate level, depending on whether the BBT3821 is
interfaced to a CX4 connection, or a XAUI/LX4 interface
(where it is assumed that the electro-optical interface is
XAUI-compatible).
Although the BBT3821 will come out of reset with CX4 or
XAUI-directed values, some of these default register settings
may need to be changed, for optimum operation in any
specific application. All of these may be set via the Auto-
Configure operation (See “Auto-Configuring Control
Registers” on page 16).
The default values of pre-emphasis and receive equalization
set by the LX4_MODE select pin may need to be adjusted,
particularly if the serial 3Gbps PCB traces on the ‘host’ side
(the XAUI or the XENPAK/XPAK/X2 side) are long, (in which
case the PHY XS values may need adjustment), or if the
connection to a CX4 connector or laser driver and photo
detector and limiting amplifier involve extra connectors, long
traces, or enhanced edge rates (in which case the PMA/D
values should be adjusted).
Recommended Analog Power and Ground Plane
Splits
The BBT3821 high-speed analog circuits as well as high-
The default value of the PMA/D and PHY XS XAUI_EN bits
is set at ‘1’, and for normal XAUI or CX4/LX4 operation, this
is usually the best setting for this use. Byte alignment will
follow the IEEE 802.3ae PCS SYNC specification, Lane
alignment will follow the DESKEW algorithm in the same
specification, and the pseudo-random /A/K/R/ generation in
IDLE will also be performed according to the same
specifications.
speed I/O draw power from the analog power (V
) and
DDA
(shared) ground GNDA pins/balls (pins or balls will be used
inter-changeably through out this document). In order for the
BBT3821 to achieve best performance, the V
and
DDA
GNDA should be kept as “quiet” as possible. There are also
70
INTERSIL [ Intersil ]
