BBT3821
FIGURE 17. MDIO TIMING AFTER SOFT RESET (D.0.15)
(Internal States,
not observable)
D.0.15
reset
Bit reset
TRSTBIT
TMDRST
1st preamble
MDIO
Engine reset, ignores
bit
engine
preamble
MDC
2
FIGURE 18. BEGINNING I C NVR READ AT THE END OF RESET
RST wait train wait
Read NVR
Read DOM
(done)
condition
TUpdate
TConfig
TTRAIN
TRESET
RSTN
SCL
SDA
TWAIT
TWAIT
Default Data
Auto-Config Data
Control Registers
2
FIGURE 19. I C BUS INTERFACE PROTOCOL
SDA
acknowledgement
signal from slave
acknowledgement
signal from receiver
MSB
byte complete,
interrupt within slave
clock line held low while
interrupts are served
S
or
Sr
Sr
or
P
SCL
1
2
7
8
9
1
2
3 - 8
9
ACK
ACK
START or
STOP or
repeated START
condition
repeated START
condition
68
INTERSIL [ Intersil ]
