BBT3821
Table 98. MANAGEMENT DATA INTERFACE PINS
PIN#
NAME
TYPE
I/O (open drain output)
Input
DESCRIPTION
P11
R11
R12
T12
P12
N12
T11
MDIO
MDC
Management Address/Data I/O. 1.2V CMOS input, 2.5V Tolerant
Management Interface Clock. 1.2V CMOS, 2.5V Tolerant, with Schmitt trigger
Management Port Address Setting 1.2V CMOS
PADR[4]
PADR[3]
PADR[2]
PADR[1]
PADR[0]
Input
Table 99. MISCELLANEOUS PINS
PIN#
NAME
TYPE
DESCRIPTION
N11
P10
B9
MF[0]
Output
Multi-function Outputs, Lanes 0 - 3. The functions of these pins are enabled via the MDIO
Interface.
1.5V CMOS
MF[1]
MF[2]
MF[3]
RSTN
The default condition for these pins is PHY XGXS BIST_ERR. See Table 81 (bits MF_SEL
and MF_CTRL) for further details.
A10
N10
Input
Chip Reset (FIFO Clear) Assert RSTN for at least 10µs from power up. Active low. Schmitt
trigger input, 1.2V CMOS, 2.5V tolerant.
23
D10
A11
BIST_ENA
Input (with pulldown) Built-In Self Test Enable- Active High. When high, enables internal 2 -1 byte PRBS test
function generator and checker. 1.5V CMOS
LX4_MODE
Input (with pulldown) CX4/LX4 Mode Select. When high, LX4 mode is selected. When low, CX4 mode is
selected. This pin decides the trigger sources of LASI, and the default pre-emphasis and
equalization strength of the high speed serial port on the PMA/PMD side. 1.5V CMOS
B11
D7
D5
D6
N8
LASI
Output (open drain) Link Alarm Status Interrupt Request. When low, pin indicates the existence of an incorrect
condition. An external 10-22kΩ pull-up to 1.2V or 1.5V is recommended. 1.2V CMOS, 2.5V
tolerant.
(1)
OPTXLBC
OPTTEMP
Input
Input
Input
Input
TX Laser Bias Current. Optical monitoring input. Active level is latched into register bit
1.36868.9 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
(1)
Transceiver Temperature. Optical monitoring input. Active level is latched into register bit
1.36868.8 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
(1)
OPTXLOP
TX Laser Output Power. Optical monitoring input. Active level is latched into register bit
1.36868.7 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
(2)
TX_FAULT
TX Fault Condition. Transmitter (Egress) external fault input. Active level is latched into
register bits 1.10 and 1.36868.6 and can be configured to trigger LASI. When this pin is not
driven by an external device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V
tolerant.
(1)
C5
OPRXOP
Input
Input
Receive Optical Power. Optical monitoring input 4. Active level is latched into register bit
1.36867.5 and can be configured to trigger LASI. When this pin is not driven by an external
device, it should be pulled inactive (default down). 1.5V CMOS, 2.5V tolerant.
(1)
(1)
(1)
(1)
A6
A5
A7
B7
D11
OPRLOS[3]
OPRLOS[2]
OPRLOS[1]
OPRLOS[0]
XP_ENA
Optical Receiver Loss Of Signal. Optical monitoring input 5 – 8. Active (loss) levels are
latched into register 1.10 and can be configured to trigger LASI. When these pins are not
driven by an external device, they should pulled inactive (default down). 1.5V CMOS, 2.5V
tolerant.
Input
XENPAK Enable. Enable XENPAK support. Active high. Activates 2-wire serial bus
interface. 1.5V CMOS, 2.5V tolerant.
56
INTERSIL [ Intersil ]
