BBT3821
Pin Specifications
Table 94. CLOCK PINS
PIN#
T9/T8
NAME
TYPE
DESCRIPTION
RFCP/RFCN
TXCLK20
Input
Differential Reference Input Clock. The reference input clock frequency is line rate
clock frequency divided by 20 (full rate mode) or 10 (half rate mode). The pins are
internally biased at VDDA/2, and should be AC coupled.
LVPECL
C10
Output
1.5V CMOS
Transmit Clock Output. Divided-by-20 transmit clock output.
Table 95. XAUI (XENPAK/XPAK/X2) SIDE SERIAL DATA PINS
PIN#
NAME
TYPE
DESCRIPTION
T14/T15
P14/P15
M14/M15
K14/K15
H14/H15
F14/F15
D14/D15
B14/B15
TXP0P/TXP0N
TXP1P/TXP1N
TXP2P/TXP2N
TXP3P/TXP3N
RXP0P/RXP0N
RXP1P/RXP1N
RXP2P/RXP2N
RXP3P/RXP3N
Output CML
Transmit Differential Pairs, Lane 0 to 3. CML High speed serial outputs.
Input CML
Receive Differential Pairs, Lane 0 to 3. CML High speed serial inputs. Differentially
terminated at 100Ω
Table 96. PMA/PMD (CX4/LX4) SIDE SERIAL DATA PINS
PIN#
A2/A3
C2/C3
E2/E3
G2/G3
R2/R3
N2/N3
L2/L3
NAME
TCX0P/TCX0N
TCX1P/TCX1N
TCX2P/TCX2N
TCX3P/TCX3N
RCX0P/RCX0N
RCX1P/RCX1N
RCX2P/RCX2N
RCX3P/RCX3N
TYPE
DESCRIPTION
Output CML
Transmit Differential Pairs, Lane 0 to 3. CML High speed serial outputs.
Input CML
Receive Differential Pairs, Lane 0 to 3. CML High speed serial inputs. Differentially
terminated at 100Ω
J2/J3
Table 97. JTAG INTERFACE PINS
PIN#
D12
NAME
TDI
TYPE
DESCRIPTION
JTAG Input Data. 1.5V CMOS
Input (with pullup)
Output (open drain)
Input (with pullup)
Input (with pulldown)
Input (with pullup)
B12
TDO
JTAG Output Data. 1.5V CMOS, 2.5V Tolerant
JTAG Mode Select. 1.5V CMOS
D8
TMS
C12
TCLK
JTAG Clock. 1.2V CMOS, 2.5V Tolerant, with Schmitt trigger
JTAG Reset. 1.5V CMOS
C8
TRSTN
55
INTERSIL [ Intersil ]
