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5962-9054304MQA 参数 Datasheet PDF下载

5962-9054304MQA图片预览
型号: 5962-9054304MQA
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS高性能可编程DMA控制器 [CMOS High Performance Programmable DMA Controller]
分类和应用: 控制器
文件页数/大小: 25 页 / 161 K
品牌: INTERSIL [ Intersil ]
 浏览型号5962-9054304MQA的Datasheet PDF文件第6页浏览型号5962-9054304MQA的Datasheet PDF文件第7页浏览型号5962-9054304MQA的Datasheet PDF文件第8页浏览型号5962-9054304MQA的Datasheet PDF文件第9页浏览型号5962-9054304MQA的Datasheet PDF文件第11页浏览型号5962-9054304MQA的Datasheet PDF文件第12页浏览型号5962-9054304MQA的Datasheet PDF文件第13页浏览型号5962-9054304MQA的Datasheet PDF文件第14页  
82C237  
Mask Register - Each channel has associated with it a mask Status Register - The Status register is available to be read  
bit which can be set to disable an incoming DREQ. Each out of the 82C237 by the microprocessor. It contains  
mask bit is set when its associated channel produces an EOP information about the status of the devices at this point. This  
if the channel is not programmed to Autoinitialize. Each bit of information includes which channels have reached a terminal  
the 4-bit Mask register may also be set or cleared separately count and which channels have pending DMA requests. Bits  
or simultaneously under software control. The entire register 0-3 are set every time a TC is reached by that channel or an  
is also set by a RESET or Master clear. This disables all hard- external EOP is applied. These bits are cleared upon RESET,  
ware DMA requests until a Clear Mask Register instruction Master Clear, and on each Status Read. Bits 4-7 are set  
allows them to occur. The instruction to separately set or clear whenever their corresponding channel is requesting service,  
the mask bits is similar in form to that used with the Request regardless of the mask bit state. If the mask bits are set, soft-  
register. Refer to the following diagram and Figure 4 for ware can poll the Status register to determine which channels  
details. When reading the Mask register, bits 4-7 will always have DREQs, and selectively clear a mask bit, thus allowing  
read as logical ones, and bits 0-3 will display the mask bits of user defined service priority. Status bits 4-7 are updated while  
channels 0-3, respectively. The 4-bits of the mask register the clock is high, and latched on the falling edge. Status Bits  
may be cleared simultaneously by using the Clear Mask Reg- 4-7 are cleared upon RESET or Master Clear.  
ister command (see software commands section).  
Status Register  
Mask Register  
7
6
5
4
3
2
1
0
BIT NUMBER  
7
6
5
4
3
2
1
0
BIT NUMBER  
1
1
1
1
1
1
1
1
Channel 0 has reached TC  
Channel 1 has reached TC  
Channel 2 has reached TC  
Channel 3 has reached TC  
Channel 0 request  
00 Select channel 0 mask bit  
01 Select channel 1 mask bit  
10 Select channel 2 mask bit  
11 Select channel 3 mask bit  
Don’t Care,  
0
1
Clear mask bit  
Set mask bit  
All four bits of the Mask register may also be written with a  
single command.  
Channel 1 request  
Channel 2 request  
7
6
5
4
3
2
1
0
BIT NUMBER  
Channel 3 request  
0
1
Clear channel 0 mask bit  
Set channel 0 mask bit  
Don’t Care,  
Write  
All Ones,  
Read  
Temporary Register - The Temporary register is used to hold  
data during memory-to-memory transfers. Following the com-  
pletion of the transfers, the last byte moved can be read by the  
microprocessor. The Temporary register always contains the  
last byte transferred in the previous memory-to-memory oper-  
ation, unless cleared by a RESET or Master Clear.  
0
1
Clear channel 1 mask bit  
Set channel 1 mask bit  
0
1
Clear channel 2 mask bit  
Set channel 2 mask bit  
0
1
Clear channel 3 mask bit  
Set channel 3 mask bit  
OPERATION  
A3  
A2  
A1  
A0  
IOR  
IOW  
Read Status Register  
Write Command Register  
Read Request Register  
Write Request Register  
Read Command Register  
Write Single Mask Bit  
Read Mode Register  
Write Mode Register  
Set First/Last F/F  
Clear First/Last F/F  
Read Temporary Register  
Master Clear  
Clear Mode Reg. Counter  
Clear Mask Register  
Read All Mask Bits  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Write All Mask Bits  
FIGURE 4. SOFTWARE COMMAND CODES AND REGISTER CODES  
4-157