82C237
16-Bit Transfer Mode Initialization - To initialize the
Software Commands
82C237 to 16-bit Transfer Mode, a specific sequence of soft-
ware commands must be written to the device immediately
after a hardware RESET or a Master Clear instruction. The
sequence to initialize 16-bit Transfer Mode is as follows:
There are special software commands which can be
executed by reading or writing to the 82C237. These com-
mands do not depend on the specific data pattern on the
data bus, but are activated by the I/O operation itself. On
read type commands, the data value is not guaranteed.
These commands are:
1) Hardware RESET or Master Clear
2) Set First/Last Flip-Flop
3) Clear First/Last Flip-Flop
Clear First/Last Flip-Flop - This command is executed prior
to writing or reading new address or word count information
to the 82C237. This command initializes the flip-flop to a
known state (low byte first) so that subsequent accesses to
register contents by the microprocessor will address upper
and lower bytes in the correct sequence.
These software commands must occur sequentially with no
communication to or from the 82C237 between commands.
Once in 16-bit mode, the device will remain in this mode until
a hardware RESET or Master Clear sets it back to normal
(8-bit) transfer mode. If this initialization sequence is not fol-
lowed exactly, the 82C237 will operate exactly like the
82C37A or the 82C237 in normal 8-bit mode.
Set First/Last Flip-Flop - This command will set the flip-flop
to select the high byte first on read and write operations to
address and word count registers.
16-Bit DMA Transfers - In 16-bit transfer mode, each DMA
channel may be programmed to perform 8-bit or 16-bit trans-
fers. Channels which are programmed to perform 8-bit trans-
fers will operate like a normal 82C37A transfer. On channels
programmed to perform 16-bit transfers, the Current
Address register, which is normally incremented or decre-
mented by one after each transfer, is incremented or decre-
Master Clear - This software instruction has the same effect
as the hardware RESET. The Command, Status, Request,
and Temporary registers, and Internal First/Last Flip-Flop
and mode register counter are cleared and the Mask register
is set. The 82C237 will enter the idle cycle.
Clear Mask Register - This command clears the mask bits mented by two after each transfer. Also, the Current Word
of all four channels, enabling them to accept DMA requests.
Count register, which is normally decremented by one after
each transfer, is decremented by two after each transfer.
Clear Mode Register Counter - Since only one address
location is available for reading the Mode registers, an inter- 16-Bit Memory-to-Memory Transfers - 16-bit memory-to-
nal two-bit counter has been included to select Mode regis- memory transfers require an external latch to temporarily
ters during read operation. To read the Mode registers, first store the 8 most significant bits of data. When 16-bit transfer
execute the Clear Mode Register Counter command, then mode is enabled, Pin 5 (DWLE) becomes an active output
do consecutive reads until the desired channel is read. Read which may be used to enable the external data latch during
order is channel 0 first, channel 3 last. The lower two bits on memory-to-memory operations. See Figure 9 for a 16-bit
all Mode registers will read as ones.
DMA application. Channels 0 and 1 operate as memory-to-
memory transfer channels. IF either channel 0 or channel 1
is programmed to perform 16-bit transfers when a memory-
to-memory transfer is initiated, the transfer will be a 16-bit
transfer. If 8-bit memory-to-memory transfers are desired
while the 82C237 is in 16-bit transfer mode, channels 0 and
1 must both be programmed for 8-bit transfers.
External EOP Operation
The EOP pin is a bidirectional, open drain pin which may be
driven by external signals to terminate DMA operation.
Because EOP is an open drain pin an external pull-up resis-
tor to V
is required. The value of the external pull-up
CC
resistor used should guarantee a rise time of less than
125ns. It is important to note that the 82C237 will not accept
external EOP signals when it is in an SI (Idle) state. The
controller must be active to latch EXT EOP. Once latched,
the EXT EOP will be acted upon during the next S2 state,
unless the 82C237 enters an idle state first. In the latter
case, the latched EOP is cleared. External EOP pulses
occurring between active DMA transfers in demand mode
will not be recognized, since the 82C237 is in an SI state.
Pin 5 DWLE Output - When the 82C237 is initialized to 16-
bit transfer mode, pin 5 is always high impedance three-
stated. This insures compatibility with the 82C37A pin 5
description. In 16-bit transfer mode, this output becomes
active and serves a dual purpose.
During the S1 cycle of a transfer, the DWLE output indicates
the data width (0 = 16-bit, 1 = 8-bit) of the active channel.
This signal may be used with the A0 output to generate a
High Byte Enable signal for use in chip select decode logic.
Since DWLE is a multiplexed pin, Data Width information
needs to be captured in an external latch on the falling edge
of ADSTB. See Figure 9 for a 16-bit DMA application.
16-Bit Transfer Mode
The 82C237 is fully software and pin for pin compatible with
the 82C37A. Therefore, the 82C237 may be used as a faster
82C37A without modifications to software or hardware. The
82C237 may be used as an 82C37A, however, the 82C237
has an additional feature in that it may be programmed to
perform 16-bit DMA transfers, thus doubling data transfer
rate. In 16-bit transfer mode the device operates the same
as in normal (8-bit) transfer mode with exceptions noted in
this section.
During memory-to-memory transfer, the DWLE output is
used to enable an external latch which temporarily stores the
8 most significant bits of data during the read-from-memory
half of the transfer. DWLE enables this byte of data onto the
data bus during the write-to-memory half of the transfer. See
Figure 9 for a 16-bit DMA application.
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INTERSIL [ Intersil ]
