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5962-9054304MQA 参数 Datasheet PDF下载

5962-9054304MQA图片预览
型号: 5962-9054304MQA
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS高性能可编程DMA控制器 [CMOS High Performance Programmable DMA Controller]
分类和应用: 控制器
文件页数/大小: 25 页 / 161 K
品牌: INTERSIL [ Intersil ]
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82C237  
registers to operate as in normal mode (Data-Width register  
Software Commands Affected by  
16-Bit Mode  
not accessible) until 16-bit transfer mode is again entered.  
The four mask bits may also be cleared simultaneously by  
using the Clear Mask Register command (see software com-  
mands section). This command has no effect on the data-  
width bits.  
Master Clear - This software instruction has the same effect  
as the hardware RESET. The Command, Status, Request,  
and Temporary registers, and Internal First/Last Flip-Flop  
and mode register counter are cleared and the Mask register  
is set. When the Master Clear instruction occurs while in 16-  
bit transfer mode, the 82C237 enters normal (8-bit) transfer  
mode in the Idle cycle.  
Temporary Register - The internal Temporary register is  
used to hold data during memory-to-memory transfers. Fol-  
lowing the completion of the transfers, the last byte moved  
can be read by the microprocessor. In the case of 16-bit  
transfers, only the least significant 8-bits of the last word  
transferred are stored in this register. The Temporary regis-  
ter always contains the last byte transferred in the previous  
memory-to-memory operation, unless cleared by a RESET  
or Master Clear.  
Clear Mask Register - This command clears the mask bits  
of all four channels, enabling them to accept DMA requests.  
This command has no effect on data-width bits in 16-bit  
transfer mode.  
OPERATION  
Read Status Register  
A3  
A2  
A1  
A0  
IOR  
IOW  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
Write Command Register  
Read Request Register  
Write Request Register  
Read Command Register  
Write Single Mask Bit (Note 1)  
Write All Data-Width Bits (Notes 1, 2)  
Read Mode Register  
Write Mode Register  
Set First/Last F/F  
Clear First/Last F/F  
Read Temporary Register  
Master Clear  
Clear Mode Reg. Counter  
Clear Mask Register  
Read All Mask/Data-Width Bits (Note 2)  
Write All Mask Bits  
NOTES:  
1. The register to be written is determined by data bit 3.  
2. Data-Width bits exist in 82C237, 16-bit mode only.  
FIGURE 5. 16-BIT MODE SOFTWARE COMMAND CODES AND REGISTER CODES  
4-160